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Generating Hardware Assertion Checkers

For Hardware Verification, Emulation, Post-Fabrication Debugging and On-Line Monitoring

Specificaties
Paperback, 280 blz. | Engels
Springer Netherlands | 0e druk, 2010
ISBN13: 9789048179220
Rubricering
Springer Netherlands 0e druk, 2010 9789048179220
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Samenvatting

Assertion-based design is a powerful new paradigm that is facilitating quality improvement in electronic design. Assertions are statements used to describe properties of the design (I.e., design intent), that can be included to actively check correctness throughout the design cycle and even the lifecycle of the product. With the appearance of two new languages, PSL and SVA, assertions have already started to improve verification quality and productivity.

This is the first book that presents an “under-the-hood” view of generating assertion checkers, and as such provides a unique and consistent perspective on employing assertions in major areas, such as: specification, verification, debugging, on-line monitoring and design quality improvement.

Specificaties

ISBN13:9789048179220
Taal:Engels
Bindwijze:paperback
Aantal pagina's:280
Uitgever:Springer Netherlands
Druk:0

Inhoudsopgave

Assertions and the Verification Landscape.- Basic Techniques Behind Assertion Checkers.- PSL and SVA Assertion Languages.- Automata for Assertion Checkers.- Construction of PSL Assertion Checkers.- Enhanced Features and Uses of PSL Checkers.- Evaluating and Verifying PSL Assertion Checkers.- Checkers for SystemVerilog Assertions.- Conclusions and Future Work.

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        Generating Hardware Assertion Checkers