Mauro Santos,
Jorge Guilherme,
Nuno Horta
Springer International Publishing
e druk, 2019
9783030159771
Logarithmic Voltage-to-Time Converter for Analog-to-Digital Signal Conversion
Specificaties
Gebonden, blz.
|
Engels
Springer International Publishing |
e druk, 2019
ISBN13: 9783030159771
Rubricering
Onderdeel van serie
Lecture Notes in Electrical Engineering
Verwachte levertijd ongeveer 9 werkdagen
Samenvatting
This book presents a novel logarithmic conversion architecture based on cross-coupled inverter. An overview of the current state of the art of logarithmic converters is given where most conventional logarithmic analog-to-digital converter architectures are derived or adapted from linear analog-to-digital converter architectures, implying the use of analog building blocks such as amplifiers. The conversion architecture proposed in this book differs from the conventional logarithmic architectures. Future possible studies on integrating calibration in the voltage to time conversion element and work on an improved conversion architecture derived from the architecture are also presented in this book.
Specificaties
ISBN13:9783030159771
Taal:Engels
Bindwijze:gebonden
Uitgever:Springer International Publishing
Inhoudsopgave
<p>Chapter 1 Introduction</p>
<p>1.1 Nonlinear Data Conversion</p>
<p>1.2 Motivation</p>
<p>1.3 Research Goals</p>
<p>1.4 Innovative Contributions</p>
<p>1.5 Achievements</p>
<p>1.6 Document Structure</p>
Chapter 2 Nonlinear A/D Converters<p></p>
<p>2.1 Floating Point Converters</p>
<p>2.2 Logarithmic Converters</p>
<p>2.2.1 Logarithmic Pipeline Converters</p>
<p>2.2.2 Two-Step Logarithmic Converters</p>
<p>2.3 Piecewise Linear Converters</p>
<p>2.4 Oversampled Converters</p>
2.4.1 Delta Converters<p></p>
<p>2.4.2 Sigma-Delta Converters</p>
<p>2.5 Nonlinear Conversion Using Pulse Width Modulation</p>
<p>2.5.1 Modified Integrating ADC</p>
<p>2.5.2 PWM Average Approximation</p>
<p>2.6 Nonlinear Conversion Using a Lookup Table</p>
<p>2.7 Other Architectures</p>
2.8 Performance Metrics and Converter Testing<p></p>
<p>2.9 Conclusions</p>
<p>Chapter 3 Proposed Logarithmic ADC</p>
<p>3.1 Proposed Logarithmic ADC Architecture</p>
<p>3.2 Voltage-to-Time Conversion Element</p>
<p>3.3 Regeneration detection</p>
<p>3.4 Sources of nonlinearity</p>
3.4.1 Offset<p></p>
<p>3.4.2 S3 switch resistance</p>
<p>3.4.3 Regeneration detection circuitry</p>
<p>3.4.4 Thermal Noise</p>
<p>3.5 Architecture Variants</p>
<p>3.5.1 Multiple Simultaneous Conversions</p>
<p>3.5.2 Polarity and magnitude independent conversion</p>
3.6 Time-to-Digital Converter<p></p>
<p>3.7 Conclusions</p>
<p>Chapter 4 Logarithmic VTC Design</p>
<p>4.1 Determination of key design parameters</p>
<p>4.1.1 Sampling capacitors</p>
<p>4.1.2 Total transconductance</p>
<p>4.1.3 Degeneration resistors</p>
<p>4.1.4 Sampling switches</p>
<p>4.1.5 Regeneration detection</p>
<p>4.2 Simulaton Results</p>
<p>4.2.1 Process variations</p>
<p>4.2.2 Input referred noise and offset</p>
<p>4.3 Conclusions</p>
<p>Chapter 5 Circuit and Layout Level Validation</p>
<p>5.1 Configuration chain</p>
<p>5.2 Frequency divider</p>
<p>5.3 Frequency output pad</p>
<p>5.4 Voltage-to-time conversion elements</p>
5.5 Phase generator<p></p>
<p>5.6 Programmable delay block</p>
<p>5.7 Common mode voltage effect on the regeneration detection voltage</p>
<p>5.8 Demonstrator integrated circuit layout</p>
<p>5.9 Simulation results</p>
<p>5.10 Conclusions</p>
<p>Chapter 6 Evaluation of the Prototype</p>
6.1 Test Platform<p></p>
<p>6.2 Test Description</p>
<p>6.3 Experimental Results</p>
<p>6.3.1 Performance comparison</p>
<p>6.4 Input range limitation</p>
<p>6.5 Conclusions</p>
<p>Chapter 7 Future Work and Conclusions</p>
7.1 Conclusions<p></p>
<p>7.2 Future Work</p>
<p>7.2.1 Calibration</p>
<p>7.2.2 Improved Conversion Method</p>
<p>References</p>
<p>1.1 Nonlinear Data Conversion</p>
<p>1.2 Motivation</p>
<p>1.3 Research Goals</p>
<p>1.4 Innovative Contributions</p>
<p>1.5 Achievements</p>
<p>1.6 Document Structure</p>
Chapter 2 Nonlinear A/D Converters<p></p>
<p>2.1 Floating Point Converters</p>
<p>2.2 Logarithmic Converters</p>
<p>2.2.1 Logarithmic Pipeline Converters</p>
<p>2.2.2 Two-Step Logarithmic Converters</p>
<p>2.3 Piecewise Linear Converters</p>
<p>2.4 Oversampled Converters</p>
2.4.1 Delta Converters<p></p>
<p>2.4.2 Sigma-Delta Converters</p>
<p>2.5 Nonlinear Conversion Using Pulse Width Modulation</p>
<p>2.5.1 Modified Integrating ADC</p>
<p>2.5.2 PWM Average Approximation</p>
<p>2.6 Nonlinear Conversion Using a Lookup Table</p>
<p>2.7 Other Architectures</p>
2.8 Performance Metrics and Converter Testing<p></p>
<p>2.9 Conclusions</p>
<p>Chapter 3 Proposed Logarithmic ADC</p>
<p>3.1 Proposed Logarithmic ADC Architecture</p>
<p>3.2 Voltage-to-Time Conversion Element</p>
<p>3.3 Regeneration detection</p>
<p>3.4 Sources of nonlinearity</p>
3.4.1 Offset<p></p>
<p>3.4.2 S3 switch resistance</p>
<p>3.4.3 Regeneration detection circuitry</p>
<p>3.4.4 Thermal Noise</p>
<p>3.5 Architecture Variants</p>
<p>3.5.1 Multiple Simultaneous Conversions</p>
<p>3.5.2 Polarity and magnitude independent conversion</p>
3.6 Time-to-Digital Converter<p></p>
<p>3.7 Conclusions</p>
<p>Chapter 4 Logarithmic VTC Design</p>
<p>4.1 Determination of key design parameters</p>
<p>4.1.1 Sampling capacitors</p>
<p>4.1.2 Total transconductance</p>
<p>4.1.3 Degeneration resistors</p>
<p>4.1.4 Sampling switches</p>
<p>4.1.5 Regeneration detection</p>
<p>4.2 Simulaton Results</p>
<p>4.2.1 Process variations</p>
<p>4.2.2 Input referred noise and offset</p>
<p>4.3 Conclusions</p>
<p>Chapter 5 Circuit and Layout Level Validation</p>
<p>5.1 Configuration chain</p>
<p>5.2 Frequency divider</p>
<p>5.3 Frequency output pad</p>
<p>5.4 Voltage-to-time conversion elements</p>
5.5 Phase generator<p></p>
<p>5.6 Programmable delay block</p>
<p>5.7 Common mode voltage effect on the regeneration detection voltage</p>
<p>5.8 Demonstrator integrated circuit layout</p>
<p>5.9 Simulation results</p>
<p>5.10 Conclusions</p>
<p>Chapter 6 Evaluation of the Prototype</p>
6.1 Test Platform<p></p>
<p>6.2 Test Description</p>
<p>6.3 Experimental Results</p>
<p>6.3.1 Performance comparison</p>
<p>6.4 Input range limitation</p>
<p>6.5 Conclusions</p>
<p>Chapter 7 Future Work and Conclusions</p>
7.1 Conclusions<p></p>
<p>7.2 Future Work</p>
<p>7.2.1 Calibration</p>
<p>7.2.2 Improved Conversion Method</p>
<p>References</p>