David Doman,
D Doman
John Wiley & Sons
e druk, 2012
9781118243046
Engineering the CMOS Library – Enhancing Digital Design Kits for Competitive Silicon
Enhancing Digital Design Kits for Competitive Silicon
Specificaties
Gebonden, 342 blz.
|
Engels
John Wiley & Sons |
e druk, 2012
ISBN13: 9781118243046
Rubricering
Verwachte levertijd ongeveer 9 werkdagen
Samenvatting
Complete with real–world case studies, examples, and suggestions for further research, this book offers a wholly unique perspective on the digital design kit. It points to hidden value in the safety margins of standard–cell libraries and shows design engineers and managers how to use this knowledge to beat the competition. Revealing how to extract value from existing std–cells and EDA tools in order to produce tighter–margined, smaller, faster, less power–hungry, and more yield–producing integrated circuits, this book will help readers become more astute designers.
Specificaties
Inhoudsopgave
PREFACE xi
<p>ACKNOWLEDGMENTS xiii</p>
<p>1 INTRODUCTION 1</p>
<p>1.1 Adding Project–Specific Functions, Drive Strengths, Views, and Corners 4</p>
<p>1.2 What Is a DDK? 5</p>
<p>2 STDCELL LIBRARIES 9</p>
<p>2.1 Lesson from the Real World: Manager′s Perspective and Engineer′s Perspective 9</p>
<p>2.2 What Is a Stdcell? 11</p>
<p>2.3 Extended Library Offerings 32</p>
<p>2.4 Boutique Library Offerings 36</p>
<p>2.5 Concepts for Further Study 37</p>
<p>3 IO LIBRARIES 39</p>
<p>3.1 Lesson from the Real World: The Manager′s Perspective and the Engineer′s Perspective 39</p>
<p>3.2 Extension Capable Architectures versus Function Complete Architectures 40</p>
<p>3.3 Electrostatic Discharge Considerations 43</p>
<p>3.4 Concepts for Further Study 50</p>
<p>4 MEMORY COMPILERS 52</p>
<p>4.1 Lesson from the Real World: The Manager′s Perspective and the Engineer′s Perspective 52</p>
<p>4.2 Single Ports, Dual Ports, and ROM: The Compiler 55</p>
<p>4.3 Nonvolatile Memories: The Block 58</p>
<p>4.4 Special–Purpose Memories: The Custom 60</p>
<p>4.5 Concepts for Further Study 62</p>
<p>5 OTHER FUNCTIONS 63</p>
<p>5.1 Lesson from the Real World: The Manager′s Perspective and the Engineer′s Perspective 63</p>
<p>5.2 Phase–Locked Loops, Power–On Resets, and Other Small–Scale Integration Analogs 66</p>
<p>5.3 Low–Power Support Structures 69</p>
<p>5.4 Stitching Structures 71</p>
<p>5.5 Hard, Firm, and Soft Boxes 75</p>
<p>5.6 Concepts for Further Study 78</p>
<p>6 PHYSICAL VIEWS 80</p>
<p>6.1 Lesson from the Real World: The Manager′s Perspective and the Engineer′s Perspective 80</p>
<p>6.2 Picking an Architecture 82</p>
<p>6.3 Measuring Density 86</p>
<p>6.4 The Need and the Way to Work with Fabrication Houses 89</p>
<p>6.5 Concepts for Further Study 92</p>
<p>7 SPICE 95</p>
<p>7.1 Lesson from the Real World: The Manager′s Perspective and the Engineer′s Perspective 95</p>
<p>7.2 Why a Tool More Than 40 Years Old Is Still Useful 99</p>
<p>7.3 Accuracy, Reality, and Why SPICE Results Must be Viewed with a Wary Eye 102</p>
<p>7.4 Sufficient Parasitics 106</p>
<p>7.5 Concepts for Further Study 107</p>
<p>8 TIMING VIEWS 109</p>
<p>8.1 Lesson from the Real World: The Manager′s Perspective and the Engineer′s Perspective 109</p>
<p>8.2 Performance Limits and Measurement 110</p>
<p>8.3 Default Versus Conditional Arcs 110</p>
<p>8.4 Break–Point Optimization 112</p>
<p>8.5 A Word on Setup and Hold 115</p>
<p>8.6 Failure Mechanisms and Roll–Off 122</p>
<p>8.7 Supporting Efficient Synthesis 124</p>
<p>8.8 Supporting Efficient Timing Closure 131</p>
<p>8.9 Design Corner Specific Timing Views 134</p>
<p>8.10 Nonlinear Timing Views are so "Old Hat" . . . 140</p>
<p>8.11 Concepts for Further Study 142</p>
<p>9 POWER VIEWS 145</p>
<p>9.1 Lesson from the Real World: The Manager′s Perspective and the Engineer′s Perspective 145</p>
<p>9.2 Timing Arcs Versus Power Arcs 147</p>
<p>9.3 Static Power 148</p>
<p>9.4 Real Versus Measured Dynamic Power 150</p>
<p>9.5 Should Power Be Built as a Monotonic Array? 153</p>
<p>9.6 Best–Case and Worst–case Power Views Versus Best–Case and Worst–Case Timing Views 155</p>
<p>9.7 Efficiently Measuring Power 156</p>
<p>9.8 Concepts for Further Study 158</p>
<p>10 NOISE VIEWS 160</p>
<p>10.1 Lesson from the Real World: The Manager′s Perspective and the Engineer′s Perspective 160</p>
<p>10.2 Noise Arcs Versus Timing and Power Arcs 162</p>
<p>10.3 The Easy Part 165</p>
<p>10.4 The Not–So–Easy Part 166</p>
<p>10.5 Concepts for Further Study 168</p>
<p>11 LOGICAL VIEWS 170</p>
<p>11.1 Lesson from the Real World: The Manager′s Perspective and the Engineer′s Perspective 170</p>
<p>11.2 Consistency Across Simulators 171</p>
<p>11.2.1 Efficient Testing 175</p>
<p>11.3 Consistency with Timing, Power & Noise Views 177</p>
<p>11.4 Concepts for Further Study 180</p>
<p>12 TEST VIEWS 181</p>
<p>12.1 Lesson from the Real World: The Manager′s Perspective and the Engineer′s Perspective 181</p>
<p>12.2 Supporting Reachability 184</p>
<p>12.3 Supporting Observability 189</p>
<p>12.4 Concepts for Further Study 191</p>
<p>13 CONSISTENCY 193</p>
<p>13.1 Lesson from the Real World: The Manager′s Perspective and the Engineer′s Perspective 193</p>
<p>13.2 Validating Views across a Library 195</p>
<p>13.3 Validating Stdcells Across a Technology Node 199</p>
<p>13.4 Validating Libraries Across Multiple Technology Nodes 204</p>
<p>13.5 Concepts for Further Study 208</p>
<p>14 DESIGN FOR MANUFACTURABILITY 209</p>
<p>14.1 Lesson from the Real World: The Manager′s Perspective and the Engineer′s Perspective 209</p>
<p>14.2 What is DFM? 211</p>
<p>14.3 Concepts for Further Study 224</p>
<p>15 VALIDATION 226</p>
<p>15.1 Lesson from the Real World: The Manager′s Perspective and the Engineer′s Perspective 226</p>
<p>15.2 Quality Levels 229</p>
<p>15.3 Concepts for Further Study 236</p>
<p>16 PLAYING WITH THE PHYSICAL DESIGN KIT: USUALLY "AT YOUR OWN RISK" 237</p>
<p>16.1 Lesson from the Real World: The Manager′s Perspective and the Engineer′s Perspective 237</p>
<p>16.2 Manipulating Models 240</p>
<p>16.3 Added Unsupported Devices 243</p>
<p>16.4 Concepts for Further Study 245</p>
<p>17 TAGGING AND REVISIONING 247</p>
<p>17.1 Lesson from the Real World: The Manager′s Perspective and the Engineer′s Perspective 247</p>
<p>17.2 Tagging and Time Stamps 248</p>
<p>17.3 Metadata, Directory Structures, and Pointers 254</p>
<p>17.4 Concepts for Further Study 258</p>
<p>18 RELEASING AND SUPPORTING 260</p>
<p>18.1 Lesson from the Real World: The Manager′s Perspective and the Engineer′s Perspective 260</p>
<p>18.2 When Is Test Silicon Needed for Verification? 263</p>
<p>18.3 Sending the Baby Out the Door 265</p>
<p>18.4 Multiple Quality Levels on the Same Design 269</p>
<p>18.5 Supporting "Bug Fixes" 271</p>
<p>18.6 Concepts for Further Study 274</p>
<p>19 OTHER TOPICS 276</p>
<p>19.1 Lesson from the Real World: The Manager′s Perspective and the Engineer′s Perspective 276</p>
<p>19.2 Supporting High–Speed Design 279</p>
<p>19.3 Supporting Low–Power Design 283</p>
<p>19.4 Supporting Third–Party Libraries 286</p>
<p>19.5 Supporting Black Box Third–Party IP (Intellectual Property) Design 289</p>
<p>19.6 Supporting Multiple Library Design 292</p>
<p>19.7 Concepts for Further Study 293</p>
<p>20 COMMUNICATIONS 295</p>
<p>20.1 Manager′s Perspective 295</p>
<p>20.2 Customer′s Perspective 298</p>
<p>20.3 Vendor′s Perspective 300</p>
<p>20.4 Engineer′s Perspective 301</p>
<p>20.5 Concepts for Further Study 302</p>
<p>20.6 Conclusions 302</p>
<p>APPENDIX I MINIMUM LIBRARY SYNTHESIS VERSUS FULL–LIBRARY SYNTHESIS OF A FOUR–BIT FLASH ADDER 305</p>
<p>APPENDIX II PERTINENT CMOS BSIM SPICE PARAMETERS WITH UNITS AND DEFAULT LEVELS 311</p>
<p>APPENDIX III DEFINITION OF TERMS 313</p>
<p>APPENDIX IV ONE POSSIBLE MEANS OF FORMALIZED</p>
<p>MONTHLY REPORTING 317</p>
<p>INDEX 319</p>
<p>ACKNOWLEDGMENTS xiii</p>
<p>1 INTRODUCTION 1</p>
<p>1.1 Adding Project–Specific Functions, Drive Strengths, Views, and Corners 4</p>
<p>1.2 What Is a DDK? 5</p>
<p>2 STDCELL LIBRARIES 9</p>
<p>2.1 Lesson from the Real World: Manager′s Perspective and Engineer′s Perspective 9</p>
<p>2.2 What Is a Stdcell? 11</p>
<p>2.3 Extended Library Offerings 32</p>
<p>2.4 Boutique Library Offerings 36</p>
<p>2.5 Concepts for Further Study 37</p>
<p>3 IO LIBRARIES 39</p>
<p>3.1 Lesson from the Real World: The Manager′s Perspective and the Engineer′s Perspective 39</p>
<p>3.2 Extension Capable Architectures versus Function Complete Architectures 40</p>
<p>3.3 Electrostatic Discharge Considerations 43</p>
<p>3.4 Concepts for Further Study 50</p>
<p>4 MEMORY COMPILERS 52</p>
<p>4.1 Lesson from the Real World: The Manager′s Perspective and the Engineer′s Perspective 52</p>
<p>4.2 Single Ports, Dual Ports, and ROM: The Compiler 55</p>
<p>4.3 Nonvolatile Memories: The Block 58</p>
<p>4.4 Special–Purpose Memories: The Custom 60</p>
<p>4.5 Concepts for Further Study 62</p>
<p>5 OTHER FUNCTIONS 63</p>
<p>5.1 Lesson from the Real World: The Manager′s Perspective and the Engineer′s Perspective 63</p>
<p>5.2 Phase–Locked Loops, Power–On Resets, and Other Small–Scale Integration Analogs 66</p>
<p>5.3 Low–Power Support Structures 69</p>
<p>5.4 Stitching Structures 71</p>
<p>5.5 Hard, Firm, and Soft Boxes 75</p>
<p>5.6 Concepts for Further Study 78</p>
<p>6 PHYSICAL VIEWS 80</p>
<p>6.1 Lesson from the Real World: The Manager′s Perspective and the Engineer′s Perspective 80</p>
<p>6.2 Picking an Architecture 82</p>
<p>6.3 Measuring Density 86</p>
<p>6.4 The Need and the Way to Work with Fabrication Houses 89</p>
<p>6.5 Concepts for Further Study 92</p>
<p>7 SPICE 95</p>
<p>7.1 Lesson from the Real World: The Manager′s Perspective and the Engineer′s Perspective 95</p>
<p>7.2 Why a Tool More Than 40 Years Old Is Still Useful 99</p>
<p>7.3 Accuracy, Reality, and Why SPICE Results Must be Viewed with a Wary Eye 102</p>
<p>7.4 Sufficient Parasitics 106</p>
<p>7.5 Concepts for Further Study 107</p>
<p>8 TIMING VIEWS 109</p>
<p>8.1 Lesson from the Real World: The Manager′s Perspective and the Engineer′s Perspective 109</p>
<p>8.2 Performance Limits and Measurement 110</p>
<p>8.3 Default Versus Conditional Arcs 110</p>
<p>8.4 Break–Point Optimization 112</p>
<p>8.5 A Word on Setup and Hold 115</p>
<p>8.6 Failure Mechanisms and Roll–Off 122</p>
<p>8.7 Supporting Efficient Synthesis 124</p>
<p>8.8 Supporting Efficient Timing Closure 131</p>
<p>8.9 Design Corner Specific Timing Views 134</p>
<p>8.10 Nonlinear Timing Views are so "Old Hat" . . . 140</p>
<p>8.11 Concepts for Further Study 142</p>
<p>9 POWER VIEWS 145</p>
<p>9.1 Lesson from the Real World: The Manager′s Perspective and the Engineer′s Perspective 145</p>
<p>9.2 Timing Arcs Versus Power Arcs 147</p>
<p>9.3 Static Power 148</p>
<p>9.4 Real Versus Measured Dynamic Power 150</p>
<p>9.5 Should Power Be Built as a Monotonic Array? 153</p>
<p>9.6 Best–Case and Worst–case Power Views Versus Best–Case and Worst–Case Timing Views 155</p>
<p>9.7 Efficiently Measuring Power 156</p>
<p>9.8 Concepts for Further Study 158</p>
<p>10 NOISE VIEWS 160</p>
<p>10.1 Lesson from the Real World: The Manager′s Perspective and the Engineer′s Perspective 160</p>
<p>10.2 Noise Arcs Versus Timing and Power Arcs 162</p>
<p>10.3 The Easy Part 165</p>
<p>10.4 The Not–So–Easy Part 166</p>
<p>10.5 Concepts for Further Study 168</p>
<p>11 LOGICAL VIEWS 170</p>
<p>11.1 Lesson from the Real World: The Manager′s Perspective and the Engineer′s Perspective 170</p>
<p>11.2 Consistency Across Simulators 171</p>
<p>11.2.1 Efficient Testing 175</p>
<p>11.3 Consistency with Timing, Power & Noise Views 177</p>
<p>11.4 Concepts for Further Study 180</p>
<p>12 TEST VIEWS 181</p>
<p>12.1 Lesson from the Real World: The Manager′s Perspective and the Engineer′s Perspective 181</p>
<p>12.2 Supporting Reachability 184</p>
<p>12.3 Supporting Observability 189</p>
<p>12.4 Concepts for Further Study 191</p>
<p>13 CONSISTENCY 193</p>
<p>13.1 Lesson from the Real World: The Manager′s Perspective and the Engineer′s Perspective 193</p>
<p>13.2 Validating Views across a Library 195</p>
<p>13.3 Validating Stdcells Across a Technology Node 199</p>
<p>13.4 Validating Libraries Across Multiple Technology Nodes 204</p>
<p>13.5 Concepts for Further Study 208</p>
<p>14 DESIGN FOR MANUFACTURABILITY 209</p>
<p>14.1 Lesson from the Real World: The Manager′s Perspective and the Engineer′s Perspective 209</p>
<p>14.2 What is DFM? 211</p>
<p>14.3 Concepts for Further Study 224</p>
<p>15 VALIDATION 226</p>
<p>15.1 Lesson from the Real World: The Manager′s Perspective and the Engineer′s Perspective 226</p>
<p>15.2 Quality Levels 229</p>
<p>15.3 Concepts for Further Study 236</p>
<p>16 PLAYING WITH THE PHYSICAL DESIGN KIT: USUALLY "AT YOUR OWN RISK" 237</p>
<p>16.1 Lesson from the Real World: The Manager′s Perspective and the Engineer′s Perspective 237</p>
<p>16.2 Manipulating Models 240</p>
<p>16.3 Added Unsupported Devices 243</p>
<p>16.4 Concepts for Further Study 245</p>
<p>17 TAGGING AND REVISIONING 247</p>
<p>17.1 Lesson from the Real World: The Manager′s Perspective and the Engineer′s Perspective 247</p>
<p>17.2 Tagging and Time Stamps 248</p>
<p>17.3 Metadata, Directory Structures, and Pointers 254</p>
<p>17.4 Concepts for Further Study 258</p>
<p>18 RELEASING AND SUPPORTING 260</p>
<p>18.1 Lesson from the Real World: The Manager′s Perspective and the Engineer′s Perspective 260</p>
<p>18.2 When Is Test Silicon Needed for Verification? 263</p>
<p>18.3 Sending the Baby Out the Door 265</p>
<p>18.4 Multiple Quality Levels on the Same Design 269</p>
<p>18.5 Supporting "Bug Fixes" 271</p>
<p>18.6 Concepts for Further Study 274</p>
<p>19 OTHER TOPICS 276</p>
<p>19.1 Lesson from the Real World: The Manager′s Perspective and the Engineer′s Perspective 276</p>
<p>19.2 Supporting High–Speed Design 279</p>
<p>19.3 Supporting Low–Power Design 283</p>
<p>19.4 Supporting Third–Party Libraries 286</p>
<p>19.5 Supporting Black Box Third–Party IP (Intellectual Property) Design 289</p>
<p>19.6 Supporting Multiple Library Design 292</p>
<p>19.7 Concepts for Further Study 293</p>
<p>20 COMMUNICATIONS 295</p>
<p>20.1 Manager′s Perspective 295</p>
<p>20.2 Customer′s Perspective 298</p>
<p>20.3 Vendor′s Perspective 300</p>
<p>20.4 Engineer′s Perspective 301</p>
<p>20.5 Concepts for Further Study 302</p>
<p>20.6 Conclusions 302</p>
<p>APPENDIX I MINIMUM LIBRARY SYNTHESIS VERSUS FULL–LIBRARY SYNTHESIS OF A FOUR–BIT FLASH ADDER 305</p>
<p>APPENDIX II PERTINENT CMOS BSIM SPICE PARAMETERS WITH UNITS AND DEFAULT LEVELS 311</p>
<p>APPENDIX III DEFINITION OF TERMS 313</p>
<p>APPENDIX IV ONE POSSIBLE MEANS OF FORMALIZED</p>
<p>MONTHLY REPORTING 317</p>
<p>INDEX 319</p>