Richard C. Li,
RCH Li
John Wiley & Sons
2e druk, 2012
9781118128497
RF Circuit Design 2e
Specificaties
Gebonden, 860 blz.
|
Engels
John Wiley & Sons |
2e druk, 2012
ISBN13: 9781118128497
Rubricering
Onderdeel van serie
Information and Communication Technology Series,
Verwachte levertijd ongeveer 9 werkdagen
Samenvatting
This revised edition immerses practicing and aspiring industry professionals in the complex world of RF design. Completely restructured and reorganized with new content, end–of–chapter exercises, illustrations, and an appendix, the book presents integral information in three complete sections exploring RF and digital circuit design; the fundamentals of differential pair and common–mode rejection ratio (CMRR); low–noise amplifier (LNA), power amplifier (PA), voltage–controlled oscillator (VCO), mixers; and much more. It is an ideal book for engineers and managers who work in RF circuit design and for courses in electrical or electronic engineering.
Specificaties
ISBN13:9781118128497
Taal:Engels
Bindwijze:gebonden
Aantal pagina's:860
Uitgever:John Wiley & Sons
Druk:2
Inhoudsopgave
PREFACE TO THE SECOND EDITION xix
<p>PART 1 DESIGN TECHNOLOGIES AND SKILLS 1</p>
<p>1 DIFFERENCE BETWEEN RF AND DIGITAL CIRCUIT DESIGN 3</p>
<p>1.1 Controversy 3</p>
<p>1.2 Difference of RF and Digital Block in a Communication System 6</p>
<p>1.3 Conclusions 9</p>
<p>1.4 Notes for High–Speed Digital Circuit Design 9</p>
<p>2 REFLECTION AND SELF–INTERFERENCE 15</p>
<p>2.1 Introduction 15</p>
<p>2.2 Voltage Delivered from a Source to a Load 16</p>
<p>2.3 Power Delivered from a Source to a Load 23</p>
<p>2.4 Impedance Conjugate Matching 33</p>
<p>2.5 Additional Effect of Impedance Matching 42</p>
<p>3 IMPEDANCE MATCHING IN THE NARROW–BAND CASE 61</p>
<p>3.1 Introduction 61</p>
<p>3.2 Impedance Matching by Means of Return Loss Adjustment 63</p>
<p>3.3 Impedance Matching Network Built by One Part 68</p>
<p>3.4 Impedance Matching Network Built by Two Parts 74</p>
<p>3.5 Impedance Matching Network Built By Three Parts 84</p>
<p>3.6 Impedance Matching When ZS Or ZL Is Not 50 85</p>
<p>3.7 Parts In An Impedance Matching Network 93</p>
<p>4 IMPEDANCE MATCHING IN THE WIDEBAND CASE 131</p>
<p>4.1 Appearance of Narrow and Wideband Return Loss on a Smith Chart 131</p>
<p>4.2 Impedance Variation Due to the Insertion of One Part Per Arm or Per Branch 136</p>
<p>4.3 Impedance Variation Due to the Insertion of Two Parts Per Arm or Per Branch 145</p>
<p>4.4 Partial Impedance Matching for an IQ (in Phase Quadrature) Modulator in a UWB (Ultra Wide Band) System 151</p>
<p>4.5 Discussion of Passive Wideband Impedance Matching Network 174</p>
<p>5 IMPEDANCE AND GAIN OF A RAW DEVICE 181</p>
<p>5.1 Introduction 181</p>
<p>5.2 Miller Effect 183</p>
<p>5.3 Small–Signal Model of a Bipolar Transistor 187</p>
<p>5.4 Bipolar Transistor with CE (Common Emitter) Configuration 190</p>
<p>5.5 Bipolar Transistor with CB (Common Base) Configuration 204</p>
<p>5.6 Bipolar Transistor with CC (Common Collector) Configuration 214</p>
<p>5.7 Small–Signal Model of a MOSFET 221</p>
<p>5.8 Similarity Between a Bipolar Transistor and a MOSFET 225</p>
<p>5.9 MOSFET with CS (Common Source) Configuration 235</p>
<p>5.10 MOSFET with CG (Common Gate) Configuration 244</p>
<p>5.11 MOSFET with CD (Common Drain) Configuration 249</p>
<p>5.12 Comparison of Transistor Configuration of Single–stage Amplifiers with Different Configurations 252</p>
<p>6 IMPEDANCE MEASUREMENT 259</p>
<p>6.1 Introduction 259</p>
<p>6.2 Scalar and Vector Voltage Measurement 260</p>
<p>6.3 Direct Impedance Measurement by a Network Analyzer 263</p>
<p>6.4 Alternative Impedance Measurement by Network Analyzer 272</p>
<p>6.5 Impedance Measurement Using a Circulator 276</p>
<p>7 GROUNDING 281</p>
<p>7.1 Implication of Grounding 281</p>
<p>7.2 Possible Grounding Problems Hidden in a Schematic 283</p>
<p>7.3 Imperfect or Inappropriate Grounding Examples 284</p>
<p>7.4 ′Zero′ Capacitor 290</p>
<p>7.5 Quarter Wavelength of Microstrip Line 300</p>
<p>8 EQUIPOTENTIALITY AND CURRENT COUPLING ON THE GROUND SURFACE 325</p>
<p>8.1 Equipotentiality on the Ground Surface 325</p>
<p>8.2 Forward and Return Current Coupling 335</p>
<p>8.3 PCB or IC Chip with Multimetallic Layers 344</p>
<p>9 LAYOUT 349</p>
<p>9.1 Difference in Layout between an Individual Block and a System 349</p>
<p>9.2 Primary Considerations of a PCB 350</p>
<p>9.3 Layout of a PCB for Testing 352</p>
<p>9.4 VIA Modeling 355</p>
<p>9.5 Runner 360</p>
<p>9.6 Parts 369</p>
<p>9.7 Free Space 371</p>
<p>10 MANUFACTURABILITY OF PRODUCT DESIGN 377</p>
<p>10.1 Introduction 377</p>
<p>10.2 Implication of 6 Design 379</p>
<p>10.3 Approaching 6 Design 383</p>
<p>10.4 Monte Carlo Analysis 386</p>
<p>11 RFIC (RADIO FREQUENCY INTEGRATED CIRCUIT) 401</p>
<p>11.1 Interference and Isolation 401</p>
<p>11.2 Shielding for an RF Module by a Metallic Shielding Box 403</p>
<p>11.3 Strong Desirability to Develop RFIC 405</p>
<p>11.4 Interference going along IC Substrate Path 406</p>
<p>11.5 Solution for Interference Coming from Sky 411</p>
<p>11.6 Common Grounding Rules for RF Module and RFIC Design 412</p>
<p>11.7 Bottlenecks in RFIC Design 414</p>
<p>11.8 Calculating of Quarter Wavelength 420</p>
<p>PART 2 RF SYSTEM 427</p>
<p>12 MAIN PARAMETERS AND SYSTEM ANALYSIS IN RF CIRCUIT DESIGN 429</p>
<p>12.1 Introduction 429</p>
<p>12.2 Power Gain 431</p>
<p>12.3 Noise 441</p>
<p>12.4 Nonlinearity 453</p>
<p>12.5 Other Parameters 480</p>
<p>12.6 Example of RF System Analysis 482</p>
<p>13 SPECIALITY OF " ZERO IF" SYSTEM 501</p>
<p>13.1 Why Differential Pair? 501</p>
<p>13.2 Can DC Offset be Blocked out by a Capacitor? 508</p>
<p>13.3 Chopping Mixer 511</p>
<p>13.4 DC Offset Cancellation by Calibration 516</p>
<p>13.5 Remark on DC Offset Cancellation 517</p>
<p>14 DIFFERENTIAL PAIRS 521</p>
<p>14.1 Fundamentals of Differential Pairs 521</p>
<p>14.2 CMRR (Common Mode Rejection Ratio) 533</p>
<p>15 RF BALUN 547</p>
<p>15.1 Introduction 547</p>
<p>15.2 Transformer Balun 549</p>
<p>15.3 LC Balun 571</p>
<p>15.4 Microstrip Line Balun 580</p>
<p>15.5 Mixing Type of Balun 583</p>
<p>16 SOC (SYSTEM–ON–A–CHIP) AND NEXT 611</p>
<p>16.1 SOC 611</p>
<p>16.2 What is Next 612</p>
<p>PART 3 INDIVIDUAL RF BLOCKS 625</p>
<p>17 LNA (LOW–NOISE AMPLIFIER) 627</p>
<p>17.1 Introduction 627</p>
<p>17.2 Single–Ended Single Device LNA 628</p>
<p>17.3 Single–Ended Cascode LNA 662</p>
<p>17.4 LNA with AGC (Automatic Gain Control) 684</p>
<p>18 MIXER 695</p>
<p>18.1 Introduction 695</p>
<p>18.2 Passive Mixer 698</p>
<p>18.3 Active Mixer 706</p>
<p>18.4 Design Schemes 717</p>
<p>19 TUNABLE FILTER 731</p>
<p>19.1 Tunable Filter in A Communication System 731</p>
<p>19.2 Coupling between two Tank Circuits 733</p>
<p>19.3 Circuit Description 738</p>
<p>19.4 Effect of Second Coupling 739</p>
<p>19.5 Performance 743</p>
<p>20 VCO (VOLTAGE–CONTROLLED OSCILLATOR) 749</p>
<p>20.1 "Three–Point" Types of Oscillator 749</p>
<p>20.2 Other Single–Ended Oscillators 755</p>
<p>20.3 VCO and PLL (Phase Lock Loop) 759</p>
<p>20.4 Design Example of a Single–Ended VCO 769</p>
<p>20.5 Differential VCO and Quad–Phases VCO 778</p>
<p>21 PA (POWER AMPLIFIER) 789</p>
<p>21.1 Classification of PA 789</p>
<p>21.2 Single–Ended PA 794</p>
<p>21.3 Single–Ended PA IC Design 798</p>
<p>21.4 Push Pull PA Design 799</p>
<p>21.5 PA with Temperature Compensation 822</p>
<p>21.6 PA with Output Power Control 823</p>
<p>21.7 Linear PA 824</p>
<p>References 828</p>
<p>Further Reading 828</p>
<p>Exercises 829</p>
<p>Answers 829</p>
<p>INDEX 833</p>
<p>PART 1 DESIGN TECHNOLOGIES AND SKILLS 1</p>
<p>1 DIFFERENCE BETWEEN RF AND DIGITAL CIRCUIT DESIGN 3</p>
<p>1.1 Controversy 3</p>
<p>1.2 Difference of RF and Digital Block in a Communication System 6</p>
<p>1.3 Conclusions 9</p>
<p>1.4 Notes for High–Speed Digital Circuit Design 9</p>
<p>2 REFLECTION AND SELF–INTERFERENCE 15</p>
<p>2.1 Introduction 15</p>
<p>2.2 Voltage Delivered from a Source to a Load 16</p>
<p>2.3 Power Delivered from a Source to a Load 23</p>
<p>2.4 Impedance Conjugate Matching 33</p>
<p>2.5 Additional Effect of Impedance Matching 42</p>
<p>3 IMPEDANCE MATCHING IN THE NARROW–BAND CASE 61</p>
<p>3.1 Introduction 61</p>
<p>3.2 Impedance Matching by Means of Return Loss Adjustment 63</p>
<p>3.3 Impedance Matching Network Built by One Part 68</p>
<p>3.4 Impedance Matching Network Built by Two Parts 74</p>
<p>3.5 Impedance Matching Network Built By Three Parts 84</p>
<p>3.6 Impedance Matching When ZS Or ZL Is Not 50 85</p>
<p>3.7 Parts In An Impedance Matching Network 93</p>
<p>4 IMPEDANCE MATCHING IN THE WIDEBAND CASE 131</p>
<p>4.1 Appearance of Narrow and Wideband Return Loss on a Smith Chart 131</p>
<p>4.2 Impedance Variation Due to the Insertion of One Part Per Arm or Per Branch 136</p>
<p>4.3 Impedance Variation Due to the Insertion of Two Parts Per Arm or Per Branch 145</p>
<p>4.4 Partial Impedance Matching for an IQ (in Phase Quadrature) Modulator in a UWB (Ultra Wide Band) System 151</p>
<p>4.5 Discussion of Passive Wideband Impedance Matching Network 174</p>
<p>5 IMPEDANCE AND GAIN OF A RAW DEVICE 181</p>
<p>5.1 Introduction 181</p>
<p>5.2 Miller Effect 183</p>
<p>5.3 Small–Signal Model of a Bipolar Transistor 187</p>
<p>5.4 Bipolar Transistor with CE (Common Emitter) Configuration 190</p>
<p>5.5 Bipolar Transistor with CB (Common Base) Configuration 204</p>
<p>5.6 Bipolar Transistor with CC (Common Collector) Configuration 214</p>
<p>5.7 Small–Signal Model of a MOSFET 221</p>
<p>5.8 Similarity Between a Bipolar Transistor and a MOSFET 225</p>
<p>5.9 MOSFET with CS (Common Source) Configuration 235</p>
<p>5.10 MOSFET with CG (Common Gate) Configuration 244</p>
<p>5.11 MOSFET with CD (Common Drain) Configuration 249</p>
<p>5.12 Comparison of Transistor Configuration of Single–stage Amplifiers with Different Configurations 252</p>
<p>6 IMPEDANCE MEASUREMENT 259</p>
<p>6.1 Introduction 259</p>
<p>6.2 Scalar and Vector Voltage Measurement 260</p>
<p>6.3 Direct Impedance Measurement by a Network Analyzer 263</p>
<p>6.4 Alternative Impedance Measurement by Network Analyzer 272</p>
<p>6.5 Impedance Measurement Using a Circulator 276</p>
<p>7 GROUNDING 281</p>
<p>7.1 Implication of Grounding 281</p>
<p>7.2 Possible Grounding Problems Hidden in a Schematic 283</p>
<p>7.3 Imperfect or Inappropriate Grounding Examples 284</p>
<p>7.4 ′Zero′ Capacitor 290</p>
<p>7.5 Quarter Wavelength of Microstrip Line 300</p>
<p>8 EQUIPOTENTIALITY AND CURRENT COUPLING ON THE GROUND SURFACE 325</p>
<p>8.1 Equipotentiality on the Ground Surface 325</p>
<p>8.2 Forward and Return Current Coupling 335</p>
<p>8.3 PCB or IC Chip with Multimetallic Layers 344</p>
<p>9 LAYOUT 349</p>
<p>9.1 Difference in Layout between an Individual Block and a System 349</p>
<p>9.2 Primary Considerations of a PCB 350</p>
<p>9.3 Layout of a PCB for Testing 352</p>
<p>9.4 VIA Modeling 355</p>
<p>9.5 Runner 360</p>
<p>9.6 Parts 369</p>
<p>9.7 Free Space 371</p>
<p>10 MANUFACTURABILITY OF PRODUCT DESIGN 377</p>
<p>10.1 Introduction 377</p>
<p>10.2 Implication of 6 Design 379</p>
<p>10.3 Approaching 6 Design 383</p>
<p>10.4 Monte Carlo Analysis 386</p>
<p>11 RFIC (RADIO FREQUENCY INTEGRATED CIRCUIT) 401</p>
<p>11.1 Interference and Isolation 401</p>
<p>11.2 Shielding for an RF Module by a Metallic Shielding Box 403</p>
<p>11.3 Strong Desirability to Develop RFIC 405</p>
<p>11.4 Interference going along IC Substrate Path 406</p>
<p>11.5 Solution for Interference Coming from Sky 411</p>
<p>11.6 Common Grounding Rules for RF Module and RFIC Design 412</p>
<p>11.7 Bottlenecks in RFIC Design 414</p>
<p>11.8 Calculating of Quarter Wavelength 420</p>
<p>PART 2 RF SYSTEM 427</p>
<p>12 MAIN PARAMETERS AND SYSTEM ANALYSIS IN RF CIRCUIT DESIGN 429</p>
<p>12.1 Introduction 429</p>
<p>12.2 Power Gain 431</p>
<p>12.3 Noise 441</p>
<p>12.4 Nonlinearity 453</p>
<p>12.5 Other Parameters 480</p>
<p>12.6 Example of RF System Analysis 482</p>
<p>13 SPECIALITY OF " ZERO IF" SYSTEM 501</p>
<p>13.1 Why Differential Pair? 501</p>
<p>13.2 Can DC Offset be Blocked out by a Capacitor? 508</p>
<p>13.3 Chopping Mixer 511</p>
<p>13.4 DC Offset Cancellation by Calibration 516</p>
<p>13.5 Remark on DC Offset Cancellation 517</p>
<p>14 DIFFERENTIAL PAIRS 521</p>
<p>14.1 Fundamentals of Differential Pairs 521</p>
<p>14.2 CMRR (Common Mode Rejection Ratio) 533</p>
<p>15 RF BALUN 547</p>
<p>15.1 Introduction 547</p>
<p>15.2 Transformer Balun 549</p>
<p>15.3 LC Balun 571</p>
<p>15.4 Microstrip Line Balun 580</p>
<p>15.5 Mixing Type of Balun 583</p>
<p>16 SOC (SYSTEM–ON–A–CHIP) AND NEXT 611</p>
<p>16.1 SOC 611</p>
<p>16.2 What is Next 612</p>
<p>PART 3 INDIVIDUAL RF BLOCKS 625</p>
<p>17 LNA (LOW–NOISE AMPLIFIER) 627</p>
<p>17.1 Introduction 627</p>
<p>17.2 Single–Ended Single Device LNA 628</p>
<p>17.3 Single–Ended Cascode LNA 662</p>
<p>17.4 LNA with AGC (Automatic Gain Control) 684</p>
<p>18 MIXER 695</p>
<p>18.1 Introduction 695</p>
<p>18.2 Passive Mixer 698</p>
<p>18.3 Active Mixer 706</p>
<p>18.4 Design Schemes 717</p>
<p>19 TUNABLE FILTER 731</p>
<p>19.1 Tunable Filter in A Communication System 731</p>
<p>19.2 Coupling between two Tank Circuits 733</p>
<p>19.3 Circuit Description 738</p>
<p>19.4 Effect of Second Coupling 739</p>
<p>19.5 Performance 743</p>
<p>20 VCO (VOLTAGE–CONTROLLED OSCILLATOR) 749</p>
<p>20.1 "Three–Point" Types of Oscillator 749</p>
<p>20.2 Other Single–Ended Oscillators 755</p>
<p>20.3 VCO and PLL (Phase Lock Loop) 759</p>
<p>20.4 Design Example of a Single–Ended VCO 769</p>
<p>20.5 Differential VCO and Quad–Phases VCO 778</p>
<p>21 PA (POWER AMPLIFIER) 789</p>
<p>21.1 Classification of PA 789</p>
<p>21.2 Single–Ended PA 794</p>
<p>21.3 Single–Ended PA IC Design 798</p>
<p>21.4 Push Pull PA Design 799</p>
<p>21.5 PA with Temperature Compensation 822</p>
<p>21.6 PA with Output Power Control 823</p>
<p>21.7 Linear PA 824</p>
<p>References 828</p>
<p>Further Reading 828</p>
<p>Exercises 829</p>
<p>Answers 829</p>
<p>INDEX 833</p>