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Digital Integrated Circuits

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Paperback, blz. | Engels
Pearson Education | e druk, 2003
ISBN13: 9780130909961
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Pearson Education e druk, 2003 9780130909961
€ 102,94
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Since the publication of the first edition of this book in 1996, CMOS manufacturing technology has continued its breathtaking pace, scaling to ever-smaller dimensions. Minimum feature sizes are now reaching the 100-rim realm. Circuits are becoming more complex, challenging the productivity of the designer, while the plunge into the deep-submicron space causes devices to behave differently and brings to the forefront a number of new issues that impact the reliability, cost, performance, power dissipation, and reliability of the digital IC. This updated text reflects the ongoing (r)evolution in the world of digital integrated circuit design, caused by this move into the deep-submicron realm. This means increased importance of deep-submicron transistor effects, interconnect, signal integrity, high-performance and low-power design, timing, and clock distribution. In contrast to the first edition, the present text focuses entirely on CMOS ICs. http://bwrc.eecs.berkeley.edu/IcBook—A Dynamic Companion

Even more than for the first edition, this book uses its companion website to evolve and grow over time. It contains complete Microsoft PowerPoint presentations covering all the material, updates. corrections, design projects, and extensive instructor material. Most importantly, all problem sets are now available on the website (and have been removed from the text). Outstanding Features of the Text It focuses solely on deep-submicron CMOS devices, the workhorses of today's digital integrated circuits. A simple transistor model for manual analysis, called the unified MOS model, has been developed and is used throughout. Design Examples stress the design of Digital ICs from a real-world perspective. Design challenges and guidelines are highlighted. 0.25-micron CMOS technology is used for all the examples and problems. Design Methodology inserts are interspersed throughout the text, highlighting the importance of methodology and tools in today's design process. A Perspective section at the end of each chapter gives an insight into future evolutions.

Specificaties

ISBN13:9780130909961
Taal:Engels
Bindwijze:Paperback

Inhoudsopgave

(NOTE: Each chapter begins with an Introduction and concludes with a Summary, To Probe Further, and Exercises and Design Problems.) <p> I. THE FABRICS. </p> <div style="margin-left: 0.2in;"> 1. Introduction. </div> <br> <p> </p> <div style="margin-left: 0.4in;"> A Historical Perspective. Issues in Digital Integrated Circuit Design. Quality Metrics of a Digital Design. </div> <p></p> <div style="margin-left: 0.2in;"> 2. The Manufacturing Process. </div> <br> <p> </p> <div style="margin-left: 0.4in;"> The CMOS Manufacturing Process. Design Rules—The Contract between Designer and Process Engineer. Packaging Integrated Circuits. Perspective—Trends in Process Technology. </div> <p></p> <div style="margin-left: 0.2in;"> 3. The Devices. </div> <br> <p> </p> <div style="margin-left: 0.4in;"> The Diode. The MOS(FET) Transistor. A Word on Process Variations. Perspective: Technology Scaling. </div> <p></p> <div style="margin-left: 0.2in;"> 4. The Wire. </div> <br> <p> </p> <div style="margin-left: 0.4in;"> A First Glance. Interconnect Parameters—Capitance, Resistance, and Inductance. Electrical Wire Models. SPICE Wire Models. Perspective: A Look into the Future. </div> <p></p> <p> II. A CIRCUIT PERSPECTIVE. </p> <div style="margin-left: 0.2in;"> 5. The CMOS Inverter. </div> <br> <p> </p> <div style="margin-left: 0.4in;"> The Static CMOS Inverter—An Intuitive Perspective. Evaluating the Robustness of the CMOS Inverter: The Static Behavior. Performance of CMOS Inverter: The Dynamic Behavior. Power, Energy, and Energy-Delay. Perspective: Technology Scaling and Its Impact on the Inverter Metrics. </div> <p></p> <div style="margin-left: 0.2in;"> 6. Designing Combinational Logic Gates in CMOS. </div> <br> <p> </p> <div style="margin-left: 0.4in;"> Static CMOS Design. Dynamic CMOS Design. How to Choose a Logic Style? Perspective: Gate Design in the Ultra Deep-Submicron Era. </div> <p></p> <div style="margin-left: 0.2in;"> 7. Designing Sequential Logic Circuits. </div> <br> <p> </p> <div style="margin-left: 0.4in;"> Timing Metrics for Sequential Circuits. Classification of Memory Elements. Static Latches and Registers. Dynamic Latches and Registers. Pulse Registers. Sense-Amplifier Based Registers. Pipelining: An Approach to Optimize Sequential Circuits. Non-Bistable Sequential Circuits. Perspective: Choosing a Clocking Strategy. </div> <p></p> <p> III. A SYSTEM PERSPECTIVE. </p> <div style="margin-left: 0.2in;"> 8. Implementation Strategies for Digital ICS. </div> <br> <p> </p> <div style="margin-left: 0.4in;"> From Custom to Semicustom and Structured-Array Design Approaches. Custom Circuit Design. Cell-Based Design Methodology. Array-Based Implementation Approaches. Perspective—The Implementation Platform of the Future. </div> <p></p> <div style="margin-left: 0.2in;"> 9. Coping with Interconnect. </div> <br> <p> </p> <div style="margin-left: 0.4in;"> Capacitive Parasitics. Resistive Parasitics. Inductive Parasitics. Advanced Interconnect Techniques. Perspective: Networks-on-a-Chip. </div> <p></p> <div style="margin-left: 0.2in;"> 10. Timing Issues in Digital Circuits. </div> <br> <p> </p> <div style="margin-left: 0.4in;"> Timing Classification of Digital Systems. Synchronous Design—An In-Depth Perspective. Self-Timed Circuit Design. Synchronizers and Arbiters. Clock Synthesis and Synchronization Using a Phased-Locked Loop. Future Directions and Perspectives. </div> <p></p> <div style="margin-left: 0.2in;"> 11. Designing Arithmetic Building Blocks. </div> <br> <p> </p> <div style="margin-left: 0.4in;"> Datapaths in Digital Processor Architectures. The Adder. The Multiplier. The Shifter. Other Arithmetic Operators. Power and Spped Trade-Offs in Datapath Structures. Perspective: Design as a Trade-off. </div> <p></p> <div style="margin-left: 0.2in;"> 12. Designing Memory and Array Structures. </div> <br> <p> </p> <div style="margin-left: 0.4in;"> The Memory Core. Memory Peripheral Circuitry. Memory Reliability and Yield. Power Dissipation in Memories. Case Studies in Memory Design. Perspective: Semiconductor Memory Trends and Evolutions. </div> <p></p> <div style="margin-left: 0.2in;"> Problem Solutions. </div> <br> <div style="margin-left: 0.2in;"> Index. </div> <br>
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