Three-Dimensional Integrated Circuit Design

<p>1. Introduction 2. Manufacturing of 3-D Packaged Systems 3. 3-D Integrated Circuit Fabrication Technologies 4. Electrical Modeling and Closed-Form Expressions of Through Silicon Vias 5. Substrate Noise Coupling in Heterogeneous 3-D ICs 6. Design of 3-D ICs with Inductive Links7. Interconnect Prediction Models 8. Cost Issues for 3-D Integrated Systems9. Physical Design Techniques for 3-D ICs 10. Timing Optimization for Two-Terminal Interconnects 11. Timing Optimization for Multi-Terminal Interconnects 12. Thermal Modeling and Analysis 13. Thermal Management Strategies for 3-D ICs 14. Case Study: Thermal Effects in a prototype 3-D IC 15. Three-Dimensional Networks-on-Chip 16. Synchronization in 3-D ICs 17. Case Study: Clock distribution in 3-D ICs 18. Variation Effects on 3-D ICs 19. Power Delivery and Distribution for 3-D ICs20. Case Study: Power Distribution Networks in 3-D ICs 21. Conclusions and Future Prospects</p> <p>AppendixA: Enumeration of Gate Pairs in a 3-D ICB: Formal Proof of Optimum Single Via PlacementC: Proof of the Two-Terminal Via Placement HeuristicD: Proof of Condition for Via Placement of Multi-Terminal Nets GlossaryE: Correlation of WID Variations for Intra-Tier Buffers F: Extension of the Proposed Model to Include Variations of Wires </p>