3D IC Integration and Packaging

1 3D Integration for Semiconductor IC Packaging<br/>1.1 Introduction<br/>1.2 3D Integration<br/>1.3 3D IC Packaging<br/>1.4 3D Si Integration<br/>1.5 3D IC Integration<br/>1.5.1 Hybrid Memory Cube<br/>1.5.2 Wide I/O DRAM and Wide I/O 2<br/>1.5.3 High Bandwidth Memory<br/>1.5.4 Wide I/O Memory (or Logic-on-Logic)<br/>1.5.5 Passive Interposer (2.5D IC Integration)<br/>1.6 Supply Chains before the TSV Era<br/>1.6.1 FEOL (Front-End-of-Line)<br/>1.6.2 BEOL (Back-End-of-Line)<br/>1.6.3 OSAT (Outsourced Semiconductor Assembly and Test)<br/>1.7 Supply Chains for the TSV Era—Who Makes the TSV?<br/>1.7.1 TSVs Fabricated by the Via-First Process<br/>1.7.2 TSVs Fabricated by the Via-Middle Process<br/>1.7.3 TSVs Fabricated by the Via-Last (from the Front Side) Process<br/>1.7.4 TSVs Fabricated by the Via-Last (from the Back Side) Process<br/>1.7.5 How About the Passive TSV Interposers?<br/>1.7.6 Who Wants to Fabricate the TSV for Passive Interposers?<br/>1.7.7 Summary and Recommendations<br/>1.8 Supply Chains for the TSV Era—Who Does the MEOL, Assembly, and Test?<br/>1.8.1 Wide I/O Memory (Face-to-Back) by TSV Via-Middle Fabrication Process<br/>1.8.2 Wide I/O Memory (Face-to-Face) by TSV Via-Middle Fabrication Process<br/>1.8.3 Wide I/O DRAM by TSV Via-Middle Fabrication Process<br/>1.8.4 2.5D IC Integration with TSV/RDL Passive Interposers<br/>1.8.5 Summary and Recommendations<br/>1.9 CMOS Images Sensors with TSVs<br/>1.9.1 Toshiba’s DynastronTM<br/>1.9.2 STMicroelectronics’ VGA CIS Camera Module<br/>1.9.3 Samsung’s S5K4E5YX BSI CIS<br/>1.9.4 Toshiba’s HEW4 BSI TCM5103PL<br/>1.9.5 Nemotek’s CIS<br/>1.9.6 SONY’s ISX014 Stacked Camera Sensor<br/>1.10 MEMS with TSVs<br/>1.10.1 STMicroelectronics’ MEMS Inertial Sensors<br/>1.10.2 Discera’s MEME Resonator<br/>1.10.3 Avago’s FBAR MEMS Filter<br/>1.11 References<br/>2 Through-Silicon Vias Modeling and Testing<br/>2.1 Introduction<br/>2.2 Electrical Modeling of TSVs<br/>2.2.1 Analytic Model and Equations for a Generic TSV Structure<br/>2.2.2 Verification of the Proposed TSV Model in Frequency Domain<br/>2.2.3 Verification of the Proposed TSV Model in Time Domain<br/>2.2.4 TSV Electrical Design Guideline<br/>2.2.5 Summary and Recommendations<br/>2.3 Thermal Modeling of TSVs<br/>2.3.1 Cu-Filled TSV Equivalent Thermal Conductivity Extraction<br/>2.3.2 Thermal Behavior of a TSV Cell<br/>2.3.3 Cu-Filled TSV Equivalent Thermal Conductivity Equations<br/>2.3.4 Verification of the TSV Equivalent Thermal Conductivity Equations<br/>2.3.5 Summary and Recommendations<br/>2.4 Mechanical Modeling and Testing of TSVs<br/>2.4.1 TEM between the Cu-Filled TSV and Its Surrounding Si<br/>2.4.2 Experimental Results on Cu Pumping during Manufacturing<br/>2.4.3 Cu Pumping under Thermal Shock Cycling<br/>2.4.4 Keep-Out-Zone of Cu-Filled TSVs<br/>2.4.5 Summary and Recommendations<br/>2.5 References<br/>3 Stress Sensors for Thin-Wafer Handling and Strength Measurement<br/>3.1 Introduction<br/>3.2 Design and Fabrication of Piezoresistive Stress Sensors<br/>3.2.1 Design of Piezoresistive Stress Sensors<br/>3.2.2 Fabrication of the Stress Sensors<br/>3.2.3 Summary and Recommendations<br/>3.3 Application of Stress Sensors in Thin-Wafer Handling<br/>3.3.1 Design, Fabrication, and Calibration of Piezoresistive Stress Sensors<br/>3.3.2 Stress Measurement in Wafer after Thinning<br/>3.3.3 Summary and Recommendations<br/>3.4 Application of Stress Sensors in Wafer Bumping<br/>3.4.1 Stresses after UBM Fabrication<br/>3.4.2 Stresses after Dry-Film Process<br/>3.4.3 Stresses after Solder Bumping Process<br/>3.4.4 Summary and Recommendations<br/>3.5 Application of Stress Sensors in Drop Test of Embedded Ultrathin Chips<br/>3.5.1 Test Vehicle and Fabrication<br/>3.5.2 Experimental Setup and Procedure<br/>3.5.3 In-Situ Stress Measurement Results<br/>3.5.4 Reliability Testing<br/>3.5.5 Summary and Recommendations<br/>3.6 References<br/>4 Package Substrate Technologies<br/>4.1 Introduction<br/>4.2 Package Substrate with Build-up Layers for Flip Chip 3D IC Integration<br/>4.2.1 Surface Laminate Circuit Technology<br/>4.2.2 The Trend in Package Substrate with Build-up Layers<br/>4.2.3 Summary and Recommendations<br/>4.3 Coreless Package Substrates<br/>4.3.1 Advantages and Disadvantages of Coreless Package Substrates<br/>4.3.2 Substitution of Si Interposer by Coreless Substrates<br/>4.3.3 Warpage Problem and Solution of Coreless Substrates<br/>4.3.4 Summary and Recommendations<br/>4.4 Recent Advance of Package Substrate with Build-up Layer<br/>4.4.1 Thin-Film Layers on Top of Build-up Layer of Package Substrate<br/>4.4.2 Warpage and Qualification Results<br/>4.4.3 Summary and Recommendations<br/>4.5 References<br/>5 Microbumps: Fabrication, Assembly, and Reliability<br/>5.1 Introduction<br/>5.2 Fabrication, Assembly, and Reliability of 25-μm-Pitch Microbumps<br/>5.2.1 Test Vehicle<br/>5.2.2 Structure of the Microbumps<br/>5.2.3 Structure of the ENIG Pads<br/>5.2.4 Fabrication of the 25-μm-Pitch Microbumps<br/>5.2.5 Fabrication of ENIG Bonding Pads on Si Carrier<br/>5.2.6 Thermal Compression Bonding Assembly<br/>5.2.7 Evaluation of the Underfill<br/>5.2.8 Reliability Assessment<br/>5.2.9 Summary and Recommendations<br/>5.3 Fabrication, Assembly, and Reliability of 20-μm-Pitch Microbumps<br/>5.3.1 Test Vehicle<br/>5.3.2 Assembly of Test Vehicle<br/>5.3.3 Formation of Microjoints by Thermocompression Bonding<br/>5.3.4 Microgap Filling<br/>5.3.5 Reliability Test<br/>5.3.6 Reliability Test Results and Discussion<br/>5.3.7 Failure Mechanism of the Microjoints<br/>5.3.8 Summary and Recommendations<br/>5.4 Fabrication, Assembly, and Reliability of 15-μm-Pitch Microbumps<br/>5.4.1 Microbumps and UBM Pads of the Test Vehicle<br/>5.4.2 Assembly<br/>5.4.3 Assembly with CuSn Solder Microbump and ENIG Pad<br/>5.4.4 Assembly with CuSn Solder Microbump and CuSn Solder Microbump<br/>5.4.5 Evaluation of Underfill<br/>5.4.6 Summary and Recommendations<br/>5.5 References<br/>6 3D Si Integration<br/>6.1 Introduction<br/>6.2 The Electronic Industry<br/>6.3 Moore’s Law and More-Than-Moore<br/>6.4 The Origin of 3D Integration<br/>6.5 Overview and Outlook of 3D Si Integration<br/>6.5.1 Bonding Methods for 3D Si Integration<br/>6.5.2 Cu-to-Cu (W2W) Bonding<br/>6.5.3 Cu-to-Cu (W2W) Bonding with Post-Annealing<br/>6.5.4 Cu-to-Cu (W2W) Bonding at Room Temperature<br/>6.5.5 SiO2-to-SiO2 (W2W) Bonding<br/>6.5.6 A Few Notes on W2W Bonding<br/>6.6 3D Si Integration Technology Challenges<br/>6.7 3D Si Integration EDA Challenges<br/>6.8 Summary and Recommendations<br/>6.9 References<br/>7 2.5D/3D IC Integration<br/>7.1 Introduction<br/>7.2 TSV Process for 3D IC Integration<br/>7.2.1 Tiny Vias on a Chip<br/>7.2.2 Via-First Process<br/>7.2.3 Via-Middle Process<br/>7.2.4 Via-Last from the Front-Side Process<br/>7.2.5 Via-Last from the Back-Side Process<br/>7.2.6 Summary and Recommendations<br/>7.3 The Potential Application of 3D IC Integration<br/>7.4 Memory-Chip Stacking<br/>7.4.1 The Chips<br/>7.4.2 The Potential Products<br/>7.4.3 Assembly Process<br/>7.5 Wide I/O Memory or Logic-on-Logic<br/>7.5.1 The Chips<br/>7.5.2 The Potential Products<br/>7.5.3 Assembly Process<br/>7.6 Wide I/O DRAM or Hybrid Memory Cube<br/>7.6.1 The Chips<br/>7.6.2 The Potential Products<br/>7.6.3 Assembly Process<br/>7.7 Wide I/O 2 and High Bandwidth Memory<br/>7.8 Wide I/O Interface (2.5D IC Integration)<br/>7.8.1 Real Applications of TSV/RDL Passive Interposers<br/>7.8.2 Fabrication of Interposers<br/>7.8.3 Fabrication of TSVs<br/>7.8.4 Fabrication of RDLs<br/>7.8.5 Fabrication of RDLs—Polymer/Cu-Plating Method<br/>7.8.6 Fabrication of RDLs—Cu Damascene Method<br/>7.8.7 A Note on Contact Aligner for Cu Damascene Method<br/>7.8.8 Back-Side Processing and Assembly<br/>7.8.9 Summary and Recommendations<br/>7.9 Thin-Wafer Handling<br/>7.9.1 Conventional Thin-Wafer Handling Method<br/>7.9.2 TI’s TSV-WCSP Integration Process<br/>7.9.3 TSMC’s Thin-Wafer Handling with Polymer<br/>7.9.4 TSMC’s Thin-Wafer Handling without Temporary Bonding and De-Bonding<br/>7.9.5 Thin-Wafer Handling with a Heat-Spreader Wafer<br/>7.9.6 Summary and Recommendations<br/>7.10 References<br/>8 3D IC Integration with Passive Interposer<br/>8.1 Introduction<br/>8.2 3D IC Integration with TSV/RDL Interposer<br/>8.3 TSV/RDL Interposer with Double-Sided Chip Attachments<br/>8.3.1 The Structure<br/>8.3.2 Thermal Analysis—Boundary Conditions<br/>8.3.3 Thermal Analysis—TSV Equivalent Model<br/>8.3.4 Thermal Analysis—Solder Bump/Underfill Equivalent Model<br/>8.3.5 Thermal Analysis—Results<br/>8.3.6 Thermomechanical Analysis—Boundary Conditions<br/>8.3.7 Thermomechanical Analysis—Material Properties<br/>8.3.8 Thermomechanical Analysis—Results<br/>8.3.9 Fabrication of the TSV<br/>8.3.10 Fabrication of the Interposer with Top-Side RDLs<br/>8.3.11 TSV Reveal of the Cu-Filled Interposer with Top-Side RDLs<br/>8.3.12 Fabrication of the Interposer with Bottom-Side RDLs<br/>8.3.13 Passive Electrical Characterization of the Interposer<br/>8.3.14 Final Assembly<br/>8.3.15 Summary and Recommendations<br/>8.4 TSV Interposer with Chips on Both Sides<br/>8.4.1 The Structure<br/>8.4.2 Thermal Analysis—Material Properties<br/>8.4.3 Thermal Analysis—Boundary Conditions<br/>8.4.4 Thermal Analysis—Result and Discussions<br/>8.4.5 Thermomechanical Analysis—Material Properties<br/>8.4.6 Thermomechanical Analysis—Boundary Conditions<br/>8.4.7 Thermomechanical Analysis—Results and Discussions<br/>8.4.8 Interposer Fabrication<br/>8.4.9 Microbump Wafer Bumping<br/>8.4.10 Final Assembly<br/>8.4.11 Summary and Recommendations<br/>8.5 Low-Cost TSH Interposer for 3D IC Integration<br/>8.5.1 The New Design<br/>8.5.2 Electrical Simulation<br/>8.5.3 Test Vehicle<br/>8.5.4 Top Chip with UBM/Pad and Cu Pillar<br/>8.5.5 Bottom Chip with UBM/Pad/Solder<br/>8.5.6 TSH Interposer Fabrication<br/>8.5.7 Final Assembly<br/>8.5.8 Reliability Assessments<br/>8.5.9 Summary and Recommendations<br/>8.6 References<br/>9 Thermal Management of 2.5D/3D IC Integration<b
r/>9.1 Introduction<br/>9.2 Design Philosophy<br/>9.3 The New Design<br/>9.4 Equivalent Model for Thermal Analysis<br/>9.5 Interposer with Chip/Heat Spreader on Its Top Side and Chip on Its Bottom Side<br/>9.5.1 The Structure<br/>9.5.2 Material Properties<br/>9.5.3 Boundary Conditions<br/>9.5.4 Simulation Results<br/>9.6 Interposer with Chip/Heat Spreader on Its Top Side and Chip/Heat Slug on Its Bottom Side<br/>9.6.1 The Structure and Boundary Conditions<br/>9.6.2 Simulation Results<br/>9.7 Interposer with Four Chips on Its Top Side with Heat Spreader<br/>9.7.1 The Structure<br/>9.7.2 Boundary Conditions<br/>9.7.3 Simulation Results<br/>9.7.4 Summary and Recommendations<br/>9.8 Thermal Performance between 2.5D and 3D IC Integrations<br/>9.8.1 The Structures<br/>9.8.2 The Finite Element Models<br/>9.8.3 Material Properties and Boundary Conditions<br/>9.8.4 Simulation Results—Low-Power Applications<br/>9.8.5 Simulation Results—High-Power Applications<br/>9.8.6 Summary and Recommendations<br/>9.9 Thermal Management System with TSV Interposers with Embedded Microchannels<br/>9.9.1 The Structure<br/>9.9.2 Adaptor<br/>9.9.3 Heat Exchanger<br/>9.9.4 Carriers<br/>9.9.5 System Integration<br/>9.9.6 Theoretical Analysis of the Pressure Drop<br/>9.9.7 Experimental Process<br/>9.9.8 Results and Discussions<br/>9.9.9 Summary and Recommendations<br/>9.10 References<br/>10 Embedded 3D Hybrid Integration<br/>10.1 Introduction<br/>10.2 Trends of Optoelectronic Products<br/>10.3 The Old Design—High-Frequency Data Link on PCB Using Optical Waveguides<br/>10.3.1 Polymer Optical Waveguide<br/>10.3.2 Simulations—Optical Coupling Models<br/>10.3.3 Simulations—System Link Design<br/>10.3.4 Assembly of the OECB<br/>10.3.5 Measurement Results of the OECB<br/>10.3.6 Summary and Recommendations<br/>10.4 The Old Design—Embedded Board-Level Optical Interconnects<br/>10.4.1 Fabrication of Polymer Waveguide<br/>10.4.2 Fabrication of the 45° Micro-Mirror<br/>10.4.3 Assembly Process of the OECB<br/>10.4.4 Fabrication Process of Vertical-Optical Channel<br/>10.4.5 Final Assembly<br/>10.4.6 Summary and Recommendations<br/>10.5 The New Designs<br/>10.6 An Embedded 3D Hybrid Integration Design Example<br/>10.6.1 Optical Design, Analysis, and Results<br/>10.6.2 Thermal Design, Analysis, and Results<br/>10.6.3 Mechanical Design, Analysis, and Results<br/>10.6.4 Summary and Recommendations<br/>10.7 Semi-Embedded TSV Interposer with Stress Relief Gap<br/>10.7.1 Design Philosophy<br/>10.7.2 Problem Definition<br/>10.7.3 Semi-Embedded TSV Interposer Subjected to Operating Condition<br/>10.7.4 Semi-Embedded TSV Interposer Subjected to an Environmental Condition<br/>10.7.5 Summary and Recommendations<br/>10.8 References<br/>11 3D LED and IC Integration<br/>11.1 Introduction<br/>11.2 Status and Outlook of Haitz’s Law<br/>11.3 LED Has Come a Long Way!<br/>11.4 Four Key Segments of LED Products<br/>11.4.1 Substrates for LED Epitaxial Deposition<br/>11.4.2 LED Device Fabrication<br/>11.4.3 Packaging Assembly and Test of LED<br/>11.4.4 LED Final Product Assembly<br/>11.4.5 Outlook of LED Products<br/>11.5 3D LED and IC Integration<br/>11.5.1 HP FCLED and Thin-Film FCLED<br/>11.5.2 3D LED and IC Integration Packages<br/>11.5.3 Manufacturing Process of 3D LED and IC Integration<br/>11.5.4 Summary and Recommendations<br/>11.6 2.5D IC and LED Integration<br/>11.6.1 LED Packaging Using Si-Substrate with Cavities and Cu-Filled TSVs<br/>11.6.2 Si-Substrate with Cavity and TSVs for LED Packaging<br/>11.6.3 LED Wafer-Level Packaging<br/>11.6.4 Summary and Recommendation<br/>11.7 Thermal Management of 3D LED and IC Integration<br/>11.7.1 The New Designs<br/>11.7.2 3D IC and LED Integration: A Design Example<br/>11.7.3 Boundary-Value Problem<br/>11.7.4 Simulation Results (Channel Height = 700 μm)<br/>11.7.5 Simulation Results (Channel Height = 350 μm)<br/>11.7.6 Summary and Recommendations<br/>11.8 References<br/>12 3D MEMS and IC Integration<br/>12.1 Introduction<br/>12.2 MEMS Packaging<br/>12.3 Design of 3D MEMS and IC Integration<br/>12.3.1 3D MEMS and IC Integration with Lateral Electrical Feed-Through<br/>12.3.2 3D MEMS and IC Integration with Vertical Electrical Feed-Through in ASIC<br/>12.3.3 3D MEMS and IC Integration with Vertical Electrical Feed-Through in the Package Cap<br/>12.3.4 3D MEMS and IC Integration with MEMS on ASIC with TSVs<br/>12.3.5 2.5D/2.25D MEMS and IC Integration<br/>12.4 Assembly Process of 3D MEMS and IC Integration<br/>12.4.1 3D MEMS and IC Integration with Lateral Electrical Feed-Through<br/>12.4.2 3D MEMS and IC Integration with Vertical Electrical Feed-Through in ASIC<br/>12.4.3 3D MEMS and IC Integration with Vertical Electrical Feed-Through in Package Cap<br/>12.4.4 A Note on Case 10—A Real 3D MEMS and IC Integration<br/>12.4.5 Summary and Recommendations<br/>12.5 Low-Temperature Bonding of 3D MEMS Packaging with Solders<br/>12.5.1 3D IC and MEMS Integration with Different Chip Sizes<br/>12.5.2 Cavity and TSVs in Cap Wafer<br/>12.5.3 MEMS Chip to ASIC Wafer (C2W) Bonding<br/>12.5.4 ASIC Wafer with MEMS Chips to Cap Wafer (W2W) Bonding<br/>12.5.5 Summary and Recommendations<br/>12.6 Recent Developments in Advanced MEMS Packaging<br/>12.6.1 TSVs for Wafer-Level Packaging of RF MEMS Devices<br/>12.6.2 Zero-Level Packaging for RF-MEMS Implementing TSVs and Metal Bonding<br/>12.6.3 MEMS Package Based on Si-Interposer Wafer with Cu-Filled TSVs<br/>12.6.4 Wafer-Scale Packaging for FBAR-Based Oscillators<br/>12.6.5 Summary and Recommendations<br/>12.7 References<br/>13 3D CMOS Image Sensor and IC Integration<br/>13.1 Introduction<br/>13.2 FI-CIS and BI-CIS<br/>13.3 3D CIS and IC Stacking<br/>13.3.1 The Structure<br/>13.3.2 Fabrication of the CIS Pixel Wafer and Logic IC Wafer<br/>13.4 3D CIS and IC Integration<br/>13.4.1 The Structure<br/>13.4.2 Fabrication Process Flow of the Coprocessor Wafer<br/>13.4.3 Fabrication Process Flow of the CIS Wafer<br/>13.4.4 Final Assembly<br/>13.5 Summary and Recommendations<br/>13.6 References<br/>14 3D IC Packaging<br/>14.1 Introduction<br/>14.2 Chip Stacking by Wirebonding<br/>14.2.1 Au Wire<br/>14.2.2 Cu Wire and Ag Wire<br/>14.3 Package-on-Package (PoP)<br/>14.3.1 Wirebonding PoP<br/>14.3.2 Flip Chip PoP<br/>14.3.3 Wirebonding Package on Flip Chip Package<br/>14.3.4 PoP in iPhone 5s<br/>14.4 Wafer-Level Packaging<br/>14.4.1 Fan-In WLP<br/>14.4.2 3D Chip-to-Chip WLP<br/>14.5 Fan-Out eWLP<br/>14.5.1 Fan-Out eWLP<br/>14.5.2 3D eWLP—Two-Chip Stacking<br/>14.5.3 3D eWLP—Chip on eWLP (Face-to-Face)<br/>14.5.4 3D eWLP—Chip on eWLP (Face-to-Back)<br/>14.5.5 3D eWLP—Package on eWLP<br/>14.5.6 3D eWLP—eWLP on eWLP<br/>14.6 Embedded Panel-Level Packaging<br/>14.6.1 Advantages and Disadvantages<br/>14.6.2 Various Chip-Embedding Processes<br/>14.6.3 Embedded Chip in SiP Rigid Substrate<br/>14.6.4 3D Embedded Chip in SiP Flexible Substrate<br/>14.6.5 3D Embedded Stacking Chips in SiP Flexible Substrate<br/>14.7 Summary and Recommendations<br/>14.8 References<br/>Index