Nanoscale CMOS – Innovative Materials Modeling and Characterization

<p>Introduction xv<br /> F. BALESTRA</p>
<p>PART 1. NOVEL MATERIALS FOR NANOSCALE CMOS 1</p>
<p>Chapter 1. Introduction to Part 1 3<br /> D. LEADLEY, A. DOBBIE, V. SHAH and J. PARSONS</p>
<p>1.1. Nanoscale CMOS requirements 3</p>
<p>1.2. The gate stack high–— dielectrics 5</p>
<p>1.3. Strained channels 7</p>
<p>1.4. Source–drain contacts 16</p>
<p>1.5. Bibliography 17</p>
<p>Chapter 2. Gate Stacks 23<br /> O. ENGSTR&Ouml;M, I. Z. MITROVIC, S. HALL, P. K. HURLEY, K. CHERKAOUI, S. MONAGHAN, H. D. B. GOTTLOB and M. C. LEMME</p>
<p>2.1. Gate–channel coupling in MOSFETs 23</p>
<p>2.2. Properties of dielectrics 24</p>
<p>2.3. Interfaces states and bulk oxide traps 29</p>
<p>2.4. Two ternary compounds: GdSiO and LaSiO 39</p>
<p>2.5. Metal gate technology 50</p>
<p>2.6. Future outlook 56</p>
<p>2.7. Bibliography 58</p>
<p>Chapter 3. Strained Si and Ge Channels 69<br /> D. LEADLEY, A. DOBBIE, M. MYRONOV, V. SHAH and E. PARKER</p>
<p>3.1. Introduction 69</p>
<p>3.2. Relaxation of strained layers 74</p>
<p>3.3. High Ge composition Si1 xGex buffers&nbsp; 83</p>
<p>3.4. Ge channel devices 105</p>
<p>3.5. Acknowledgements 115</p>
<p>3.6. Bibliography 115</p>
<p>Chapter 4. From Thin Si/SiGe Buffers to SSOI 127<br /> S. MANTL and D. BUCA</p>
<p>4.1. Introduction 128</p>
<p>4.2. Nucleation of dislocations 129</p>
<p>4.3. Strain relaxation and strain transfer mechanisms 131</p>
<p>4.4. Overgrowth of strained Si and layer optimization 134</p>
<p>4.5. Characterization of the elastic strain 137</p>
<p>4.6. SSOI wafer fabrication 141</p>
<p>4.7. SSOI as channel material for MOSFET devices 145</p>
<p>4.8. Summary 152</p>
<p>4.9. Bibliography 153</p>
<p>Chapter 5. Introduction to Schottky–Barrier MOS Architectures: Concept, Challenges, Material Engineering and Device Integration 157<br /> E. DUBOIS, G. LARRIEU, R VALENTIN, N. BREIL and F. DANNEVILLE</p>
<p>5.1. Introduction 157</p>
<p>5.2. Challenges associated with the source/drain extrinsic contacts 158</p>
<p>5.3. Extraction of low Schottky barriers 166</p>
<p>5.4. Modulation of Schottky barrier height using low temperature dopant segregation 177</p>
<p>5.5. State–of–the–art device integration 191</p>
<p>5.6. Conclusion 195</p>
<p>5.7. Acknowledgements 197</p>
<p>5.8. Bibliography 197</p>
<p>PART 2. ADVANCED MODELING AND SIMULATION FOR NANO–MOSFETS AND BEYOND–CMOS DEVICES 205</p>
<p>Chapter 6. Introduction to Part 2 207<br /> E. SANGIORGI</p>
<p>6.1. Modeling and simulation approaches for gate current computation 208</p>
<p>6.2. Modeling and simulation approaches for drain current computation 209</p>
<p>6.3. Modeling of end of the roadmap nMOSFET with alternative channel material 209</p>
<p>6.4. NEGF simulations of nanoscale CMOS in the effective mass approximation 210</p>
<p>6.5. Compact models for advanced CMOS devices 211</p>
<p>6.6. Beyond CMOS 211</p>
<p>6.7. Bibliography 212</p>
<p>Chapter 7. Modeling and Simulation Approaches for Gate Current Computation 213<br /> B. MAJKUSIAK, P. PALESTRI, A. SCHENK, A. S. SPINELLI, C. M. COMPAGNONI and M. LUISIER</p>
<p>7.1. Introduction 213</p>
<p>7.2. Calculation of the tunneling probability 216</p>
<p>7.3. Tunneling in nonconventional devices 228</p>
<p>7.4. Trap–assisted tunneling 237</p>
<p>7.5. Models for gate current computation in commercial TCAD 243</p>
<p>7.6. Comparison between modeling approaches 249</p>
<p>7.7. Bibliography 251</p>
<p>Chapter 8. Modeling and Simulation Approaches for Drain Current Computation 259<br /> M. VASICEK, D. ESSENI, C. FIEGNA and T. GRASSER</p>
<p>8.1. Boltzmann transport equation for MOS transistors 260</p>
<p>8.2. Method of moments 262</p>
<p>8.3. Subband macroscopic transport models 276</p>
<p>8.4. Comparison with device–SMC 278</p>
<p>8.5. Conclusions 282</p>
<p>8.6. Bibliography 283</p>
<p>Chapter 9. Modeling of End of the Roadmap nMOSFET with Alternative Channel Material 287<br /> Q. RAFHAY, R. CLERC, G. GHIBAUDO, P. PALESTRI and L. SELMI</p>
<p>9.1. Introduction: replacing silicon as channel material 287</p>
<p>9.2. State–of–the–art in the modeling of alternative channel material devices 290</p>
<p>9.3. Critical analysis of the literature using analytical models 297</p>
<p>9.4. Conclusions 327</p>
<p>9.5. Bibliography 328</p>
<p>Chapter 10. NEGF for 3D Device Simulation of Nanometric Inhomogenities 335<br /> A. MARTINEZ, A. ASENOV and M. PALA</p>
<p>10.1. Introduction 335</p>
<p>10.2. Variabilities for nanoscale CMOS 343</p>
<p>10.3. Full quantum treatment of spatial fluctuations in ultra–scaled devices 361</p>
<p>10.4. Bibliography 377</p>
<p>Chapter 11. Compact Models for Advanced CMOS Devices 381<br /> B. I&Ntilde;IGUEZ, F. LIME, A. L&Aacute;ZARO and T. A. FJELDLY</p>
<p>11.1. Introduction 381</p>
<p>11.2. Electrostatics modeling issues 385</p>
<p>11.3. Transport modeling issues 388</p>
<p>11.4. 1D compact models 390</p>
<p>11.5. Ultimate MuGFET modeling issues: ballistic current and quantum confinement 405</p>
<p>11.6. Velocity saturation and channel length modulation modeling 409</p>
<p>11.7. Hydrodynamic transport model 411</p>
<p>11.8. Charge and capacitance modeling 413</p>
<p>11.9. Short–channel effects 420</p>
<p>11.10. RF and noise modeling 434</p>
<p>11.11. Acknowledgements 437</p>
<p>11.12. Bibliography 438</p>
<p>Chapter 12. Beyond CMOS 443<br /> G. IANNACCONE, G. FIORI, S. REGGIANI and M. PALA</p>
<p>12.1. Introduction 443</p>
<p>12.2. Atomistic modeling of carbon–based FETs 444</p>
<p>12.3. Numerical simulation of CNT–FETs 447</p>
<p>12.4. Effective mass modeling of carbon nanotube FETs 451</p>
<p>12.5. CNT versus graphene nanoribbon FETs 459</p>
<p>12.6. Full–quantum treatment of elastic and inelastic scattering in Si and SiC GAA nanowire FETs 461</p>
<p>12.7. Conclusions 467</p>
<p>12.8. Bibliography 468</p>
<p>PART 3. NANOCHARACTERIZATION METHODS 471</p>
<p>Chapter 13. Introduction to Part 3 473<br /> D. FLANDRE</p>
<p>Chapter 14. Accurate Determination of Transport Parameters in Sub–65 nm MOS Transistors 475<br /> M. MOUIS and G. GHIBAUDO</p>
<p>14.1. Impact of transport on device performance in the drift–diffusion regime 476</p>
<p>14.2. Standard extraction techniques and their adaptation to short channel transistors 482</p>
<p>14.3. Alternative extraction techniques 518</p>
<p>14.4. Out of equilibrium transport 531</p>
<p>14.5. Conclusions 537</p>
<p>14.6. Bibliography 539</p>
<p>Chapter 15. Characterization of Interface Defects 545<br /> P. HURLEY, O. ENGSTR&Ouml;M, D. BAUZA and G. GHIBAUDO</p>
<p>15.1. Characterization using the capacitance–voltage (C–V) response 545</p>
<p>15.2. Characterization using the conductance–voltage (G–V) response 550</p>
<p>15.3. Charge pumping 553</p>
<p>15.4. Low frequency noise 561</p>
<p>15.5. Bibliography 566</p>
<p>Chapter 16. Strain Determination 575<br /> A. O NEILL, S. OLSEN, P. DOBROSZ, R. AGAIBY and Y. TSANG</p>
<p>16.1. Introduction 575</p>
<p>16.2. Characterization requirements 575</p>
<p>16.3. Characterization techniques 579</p>
<p>16.4. Strain description 592</p>
<p>16.5. Bibliography 598</p>
<p>Chapter 17. Wide Frequency Band Characterization 603<br /> D. FLANDRE, J.–P. RASKIN and V. KILCHYTSKA</p>
<p>17.1. Modified split–CV technique for reliable mobility extraction 604</p>
<p>17.2. Small–signal electrical characterization of FinFETs: impact of access resistances and capacitances 610</p>
<p>17.3. Substrate–related output conductance degradation 619</p>
<p>17.4. Small–signal electrical characterization of Schottky barrier MOSFETs 626</p>
<p>17.5. Bibliography 632</p>
<p>List of Authors 639</p>
<p>Index 649</p>