Allard
John Wiley & Sons
e druk, 2016
9781786300812
Power Systems–On–Chip: Practical Aspects of Design
Practical Aspects of Design
Specificaties
Gebonden, 352 blz.
|
Engels
John Wiley & Sons |
e druk, 2016
ISBN13: 9781786300812
Rubricering
Verwachte levertijd ongeveer 9 werkdagen
Samenvatting
The book gathers the major issues involved in the practical design of Power Management solutions in wireless products as Internet–of–things. Presentation is not about state–of–the–art but about appropriation of validated recent technologies by practicing engineers. The book delivers insights on major trade–offs and a presentation of examples as a cookbook. The content is segmented in chapters to make access easier for the lay–person.
Specificaties
Inhoudsopgave
<p>Preface xi</p>
<p>Introduction xv<br />Bruno ALLARD</p>
<p>Chapter 1. Control Strategies and CAD Approach 1<br />Pedro ALOU, José A. COBOS, Jesus A. OLIVER, Bruno ALLARD, Benôit LABBE, Aleksandar PRODIC and Aleksandar RADIC</p>
<p>1.1. Objectives 2</p>
<p>1.2. Operation principle of three non–isolated converters 8</p>
<p>1.2.1. Buck converter operation 8</p>
<p>1.2.2. Boost converter operation 10</p>
<p>1.2.3. Buck–boost converter operation 11</p>
<p>1.3. Power stage 13</p>
<p>1.3.1. MOSFET switching an inductive load 13</p>
<p>1.3.2. Extracting the parasitic capacitance values using simulations 18</p>
<p>1.3.3. Power–stage design issues 19</p>
<p>1.3.4. Segmented power stage and multiphase operation 21</p>
<p>1.3.5. LC filter design space 22</p>
<p>1.4. Control stage 29</p>
<p>1.4.1. Voltage–mode control of the buck converter 29</p>
<p>1.4.2. The RHP zero of the boost converter 35</p>
<p>1.4.3. Current–mode control 37</p>
<p>1.4.4. Hysteretic and sliding–mode control 40</p>
<p>1.4.5. Ripple–based controls for fast dynamics 45</p>
<p>1.4.6. V1 concept: description and applicability 52</p>
<p>1.4.7. Overview of the synchronization of asynchronous modulations 59</p>
<p>1.4.8. PFM – pulse skipping: burst modes 62</p>
<p>1.5. Minimum voltage deviation controller 63</p>
<p>1.5.1. Introduction 64</p>
<p>1.5.2. Integrated circuit implementation and experimental results 67</p>
<p>1.6. CAD tools for PwrSoC design and optimization 69</p>
<p>1.6.1. Overview of the CAD requirements 71</p>
<p>1.6.2. Loss models for integrated inductors and semiconductors 73</p>
<p>1.6.3. Optimization algorithms 82</p>
<p>1.6.4. Outcome of the optimization (topology, area, loss, fsw, detailed design) 84</p>
<p>1.6.5. Impact of technology 87</p>
<p>1.7. Conclusion 91</p>
<p>Chapter 2. Magnetic Components for Increased Power Density 93<br />Santosh KULKARNI and Cian O MATHUNA</p>
<p>2.1. Commercial and research trends towards PwrSiP and PwrSoC 96</p>
<p>2.2. Review of magnetics 104</p>
<p>2.2.1. Micro–inductor structures 104</p>
<p>2.2.2. Magnetic materials and processing for thin film integrated micro–magnetic devices 111</p>
<p>2.3. Figures of merit for performance of integrated magnetics 118</p>
<p>2.3.1. Figure of merit DC performance 118</p>
<p>2.3.2. Figure of merit and AC performance 123</p>
<p>2.4. Technology roadmap and challenges 123</p>
<p>2.4.1. Market drivers 124</p>
<p>2.4.2. PwrSoC supply chain challenges 126</p>
<p>2.4.3. PwrSoC technology platform 127</p>
<p>2.4.4. Integrated magnetic devices for PwrSoC opportunities 128</p>
<p>2.5. Conclusions 130</p>
<p>2.6. Acknowledgments 132</p>
<p>Chapter 3. Dielectric Components for Increased Power Density 133<br />Frédéric VOIRON</p>
<p>3.1. Introduction 133</p>
<p>3.2. Basics of dielectric physics 135</p>
<p>3.2.1. Forewords 135</p>
<p>3.2.2. Polarization, dipole and capacitance 135</p>
<p>3.2.3. Polarization mechanisms in dielectrics 136</p>
<p>3.2.4. Losses in dielectrics 139</p>
<p>3.3. Silicon integrated capacitors 140</p>
<p>3.3.1. Integrated capacitors for enhanced performance 141</p>
<p>3.4. Integrated capacitors for enhanced reliability 145</p>
<p>3.4.1. Dielectric processing 145</p>
<p>3.4.2. Lifetime considerations 149</p>
<p>3.5. Integrated capacitor optimization for power switching 150</p>
<p>3.5.1. Regular layout 150</p>
<p>3.5.2. Broad band modeling 150</p>
<p>3.5.3. Capacitance parasitic suppression 153</p>
<p>3.6. Conclusion 154</p>
<p>Chapter 4. On–board Power Management DC/DC Inductive Converter 157<br />Benoît LABBE and Bruno ALLARD</p>
<p>4.1. Specifications 157</p>
<p>4.1.1. Load–related requirements 158</p>
<p>4.1.2. System–related requirements 159</p>
<p>4.1.3. Power delivery network 161</p>
<p>4.2. Current–mode sliding–mode control implementation 161</p>
<p>4.2.1. System analysis: voltage regulation loops 162</p>
<p>4.2.2. System analysis: loop delay control 167</p>
<p>4.2.3. System analysis: switching frequency control 168</p>
<p>4.2.4. Design 169</p>
<p>4.2.5. Results 172</p>
<p>4.3. Conclusions . 174</p>
<p>Chapter 5. On–Chip Power Management DC/DC Switched–Capacitor Converter 179<br />Gael PILLONNET, Thomas SOUVIGNET and Bruno ALLARD</p>
<p>5.1. Topology description 180</p>
<p>5.1.1. Ratio calculation 180</p>
<p>5.1.2. Basic scheme 182</p>
<p>5.1.3. Steady–state modeling 183</p>
<p>5.2. Pros and cons 190</p>
<p>5.2.1. Key advantages 190</p>
<p>5.2.2. Main disadvantages 192</p>
<p>5.3. State–of–the–art 193</p>
<p>5.3.1. Research scope and main focus 194</p>
<p>5.3.2. Integration level 194</p>
<p>5.3.3. The point–of–load (POL) application 195</p>
<p>5.4. Design example 204</p>
<p>5.4.1. Landscape of demonstrated solutions 204</p>
<p>5.4.2. Selected architecture 207</p>
<p>Chapter 6. High–Switching Frequency Inductive DC/DC Converters 213<br />Christian MARTIN, Florian NEVEU and Bruno ALLARD</p>
<p>6.1. Context and topologies 214</p>
<p>6.1.1. Discussion on figures of merit 219</p>
<p>6.1.2. Outstanding state–of–the–art performances 224</p>
<p>6.2. Cascode power stage 225</p>
<p>6.3. High–quality decoupling 229</p>
<p>6.4. Design considerations for passive components 232</p>
<p>6.5. Integrated inductor characterization 235</p>
<p>6.5.1. Harmonic characterization 235</p>
<p>6.5.2. Time–domain characterization 237</p>
<p>6.5.3. Converter experimental characterization 242</p>
<p>6.6. Conclusion 246</p>
<p>6.7. Acknowledgments 247</p>
<p>Chapter 7. Hybrid and Multi–level Converter Topologies for On–Chip Implementation of Reduced Voltage–Swing Converters 249<br />Aleksandar PRODIC, Sheikh Mohammad AHSANUZZAMAN, Behzad MAHDAVIKHAH and Timothy MCRAE</p>
<p>7.1. Introduction 249</p>
<p>7.1.1. Inductor volume reduction through voltage swing minimization 251</p>
<p>7.2. Cascaded hybrid SC–inductive topologies 254</p>
<p>7.2.1. Merged switched–capacitor multi–phase buck (MSCB) converter 255</p>
<p>7.3. Hybrid serial input/output converters 262</p>
<p>7.3.1. HSI/O power processing efficiency and power division 265</p>
<p>7.3.2. Switched–capacitor conversion ratio 267</p>
<p>7.3.3. Passive volume and switch voltage stress 269</p>
<p>7.4. An on–chip integrated high–density power management solution for portable applications based on a multi–output switched–capacitor circuit 270</p>
<p>7.5. Multi–level and flying capacitor multi–level converters 279</p>
<p>7.6. Conclusion 282</p>
<p>Bibliography 285</p>
<p>List of Acronyms 311</p>
<p>List of Authors 315</p>
<p>Index 317</p>
<p>Introduction xv<br />Bruno ALLARD</p>
<p>Chapter 1. Control Strategies and CAD Approach 1<br />Pedro ALOU, José A. COBOS, Jesus A. OLIVER, Bruno ALLARD, Benôit LABBE, Aleksandar PRODIC and Aleksandar RADIC</p>
<p>1.1. Objectives 2</p>
<p>1.2. Operation principle of three non–isolated converters 8</p>
<p>1.2.1. Buck converter operation 8</p>
<p>1.2.2. Boost converter operation 10</p>
<p>1.2.3. Buck–boost converter operation 11</p>
<p>1.3. Power stage 13</p>
<p>1.3.1. MOSFET switching an inductive load 13</p>
<p>1.3.2. Extracting the parasitic capacitance values using simulations 18</p>
<p>1.3.3. Power–stage design issues 19</p>
<p>1.3.4. Segmented power stage and multiphase operation 21</p>
<p>1.3.5. LC filter design space 22</p>
<p>1.4. Control stage 29</p>
<p>1.4.1. Voltage–mode control of the buck converter 29</p>
<p>1.4.2. The RHP zero of the boost converter 35</p>
<p>1.4.3. Current–mode control 37</p>
<p>1.4.4. Hysteretic and sliding–mode control 40</p>
<p>1.4.5. Ripple–based controls for fast dynamics 45</p>
<p>1.4.6. V1 concept: description and applicability 52</p>
<p>1.4.7. Overview of the synchronization of asynchronous modulations 59</p>
<p>1.4.8. PFM – pulse skipping: burst modes 62</p>
<p>1.5. Minimum voltage deviation controller 63</p>
<p>1.5.1. Introduction 64</p>
<p>1.5.2. Integrated circuit implementation and experimental results 67</p>
<p>1.6. CAD tools for PwrSoC design and optimization 69</p>
<p>1.6.1. Overview of the CAD requirements 71</p>
<p>1.6.2. Loss models for integrated inductors and semiconductors 73</p>
<p>1.6.3. Optimization algorithms 82</p>
<p>1.6.4. Outcome of the optimization (topology, area, loss, fsw, detailed design) 84</p>
<p>1.6.5. Impact of technology 87</p>
<p>1.7. Conclusion 91</p>
<p>Chapter 2. Magnetic Components for Increased Power Density 93<br />Santosh KULKARNI and Cian O MATHUNA</p>
<p>2.1. Commercial and research trends towards PwrSiP and PwrSoC 96</p>
<p>2.2. Review of magnetics 104</p>
<p>2.2.1. Micro–inductor structures 104</p>
<p>2.2.2. Magnetic materials and processing for thin film integrated micro–magnetic devices 111</p>
<p>2.3. Figures of merit for performance of integrated magnetics 118</p>
<p>2.3.1. Figure of merit DC performance 118</p>
<p>2.3.2. Figure of merit and AC performance 123</p>
<p>2.4. Technology roadmap and challenges 123</p>
<p>2.4.1. Market drivers 124</p>
<p>2.4.2. PwrSoC supply chain challenges 126</p>
<p>2.4.3. PwrSoC technology platform 127</p>
<p>2.4.4. Integrated magnetic devices for PwrSoC opportunities 128</p>
<p>2.5. Conclusions 130</p>
<p>2.6. Acknowledgments 132</p>
<p>Chapter 3. Dielectric Components for Increased Power Density 133<br />Frédéric VOIRON</p>
<p>3.1. Introduction 133</p>
<p>3.2. Basics of dielectric physics 135</p>
<p>3.2.1. Forewords 135</p>
<p>3.2.2. Polarization, dipole and capacitance 135</p>
<p>3.2.3. Polarization mechanisms in dielectrics 136</p>
<p>3.2.4. Losses in dielectrics 139</p>
<p>3.3. Silicon integrated capacitors 140</p>
<p>3.3.1. Integrated capacitors for enhanced performance 141</p>
<p>3.4. Integrated capacitors for enhanced reliability 145</p>
<p>3.4.1. Dielectric processing 145</p>
<p>3.4.2. Lifetime considerations 149</p>
<p>3.5. Integrated capacitor optimization for power switching 150</p>
<p>3.5.1. Regular layout 150</p>
<p>3.5.2. Broad band modeling 150</p>
<p>3.5.3. Capacitance parasitic suppression 153</p>
<p>3.6. Conclusion 154</p>
<p>Chapter 4. On–board Power Management DC/DC Inductive Converter 157<br />Benoît LABBE and Bruno ALLARD</p>
<p>4.1. Specifications 157</p>
<p>4.1.1. Load–related requirements 158</p>
<p>4.1.2. System–related requirements 159</p>
<p>4.1.3. Power delivery network 161</p>
<p>4.2. Current–mode sliding–mode control implementation 161</p>
<p>4.2.1. System analysis: voltage regulation loops 162</p>
<p>4.2.2. System analysis: loop delay control 167</p>
<p>4.2.3. System analysis: switching frequency control 168</p>
<p>4.2.4. Design 169</p>
<p>4.2.5. Results 172</p>
<p>4.3. Conclusions . 174</p>
<p>Chapter 5. On–Chip Power Management DC/DC Switched–Capacitor Converter 179<br />Gael PILLONNET, Thomas SOUVIGNET and Bruno ALLARD</p>
<p>5.1. Topology description 180</p>
<p>5.1.1. Ratio calculation 180</p>
<p>5.1.2. Basic scheme 182</p>
<p>5.1.3. Steady–state modeling 183</p>
<p>5.2. Pros and cons 190</p>
<p>5.2.1. Key advantages 190</p>
<p>5.2.2. Main disadvantages 192</p>
<p>5.3. State–of–the–art 193</p>
<p>5.3.1. Research scope and main focus 194</p>
<p>5.3.2. Integration level 194</p>
<p>5.3.3. The point–of–load (POL) application 195</p>
<p>5.4. Design example 204</p>
<p>5.4.1. Landscape of demonstrated solutions 204</p>
<p>5.4.2. Selected architecture 207</p>
<p>Chapter 6. High–Switching Frequency Inductive DC/DC Converters 213<br />Christian MARTIN, Florian NEVEU and Bruno ALLARD</p>
<p>6.1. Context and topologies 214</p>
<p>6.1.1. Discussion on figures of merit 219</p>
<p>6.1.2. Outstanding state–of–the–art performances 224</p>
<p>6.2. Cascode power stage 225</p>
<p>6.3. High–quality decoupling 229</p>
<p>6.4. Design considerations for passive components 232</p>
<p>6.5. Integrated inductor characterization 235</p>
<p>6.5.1. Harmonic characterization 235</p>
<p>6.5.2. Time–domain characterization 237</p>
<p>6.5.3. Converter experimental characterization 242</p>
<p>6.6. Conclusion 246</p>
<p>6.7. Acknowledgments 247</p>
<p>Chapter 7. Hybrid and Multi–level Converter Topologies for On–Chip Implementation of Reduced Voltage–Swing Converters 249<br />Aleksandar PRODIC, Sheikh Mohammad AHSANUZZAMAN, Behzad MAHDAVIKHAH and Timothy MCRAE</p>
<p>7.1. Introduction 249</p>
<p>7.1.1. Inductor volume reduction through voltage swing minimization 251</p>
<p>7.2. Cascaded hybrid SC–inductive topologies 254</p>
<p>7.2.1. Merged switched–capacitor multi–phase buck (MSCB) converter 255</p>
<p>7.3. Hybrid serial input/output converters 262</p>
<p>7.3.1. HSI/O power processing efficiency and power division 265</p>
<p>7.3.2. Switched–capacitor conversion ratio 267</p>
<p>7.3.3. Passive volume and switch voltage stress 269</p>
<p>7.4. An on–chip integrated high–density power management solution for portable applications based on a multi–output switched–capacitor circuit 270</p>
<p>7.5. Multi–level and flying capacitor multi–level converters 279</p>
<p>7.6. Conclusion 282</p>
<p>Bibliography 285</p>
<p>List of Acronyms 311</p>
<p>List of Authors 315</p>
<p>Index 317</p>