Katarzyna Radecka,
Zeljko Zilic
Springer US
2003e druk, 2003
9781402076527
Verification by Error Modeling
Using Testing Techniques in Hardware Verification
Specificaties
Gebonden, 216 blz.
|
Engels
Springer US |
2003e druk, 2003
ISBN13: 9781402076527
Rubricering
Onderdeel van serie
Frontiers in Electronic Testing
Levertijd ongeveer 8 werkdagen
Samenvatting
This book presents the basis for reusing the test vector generation and simulation for the purpose of implementation verification, to result in a significant timesaving. It brings the results in the direction of merging manufacturing test vector generation and verification.
Specificaties
ISBN13:9781402076527
Taal:Engels
Bindwijze:gebonden
Aantal pagina's:216
Uitgever:Springer US
Druk:2003
Inhoudsopgave
1: Introduction. 1. Design flow. 2. Verification - approaches and problems. 3. Book objectives.
2: Boolean function representations. 1. Background - function representations. 2. Decision diagrams. 3. Spectral representations. 4. Arithmetic transform.
3: Don't cares and their calculation. 1. Incompletely specified Boolean functions. 2. Using don't cares for redundancy identification.
4: Testing. 1. Introduction. 2. Fault list reduction. 3. Overview of simulators. 4. Fault simulators. 5. Deterministic vector generation - ATPG. 6. Conclusions.
5: Design error models. 1. Introduction. 2. Design errors. 3. Explicit design error models. 4. Implicit error model precursors. 5. Additive implicit error model. 6. Design error detection and correction. 7. Conclusions.
6: Design verification by AT. 1. Introduction. 2. Detecting small AT errors. 3. Bounding error by Walsh transform. 4. Experimental results. 5. Conclusions.
7: Identifying redundant gate and wire replacements. 1. Introduction. 2. Gate replacement faults. 3. Redundancy detection by don't cares. 4.Exact redundant fault identification. 5. Identifying redundant wire replacements. 6. Exact wire redundancy identification. 7. I/O port replacement detection. 8. Experimental results. 9. Conclusions. Conclusions and furtherwork. 1. Conclusions. 2. Future work.
Appendices. References. Index.
2: Boolean function representations. 1. Background - function representations. 2. Decision diagrams. 3. Spectral representations. 4. Arithmetic transform.
3: Don't cares and their calculation. 1. Incompletely specified Boolean functions. 2. Using don't cares for redundancy identification.
4: Testing. 1. Introduction. 2. Fault list reduction. 3. Overview of simulators. 4. Fault simulators. 5. Deterministic vector generation - ATPG. 6. Conclusions.
5: Design error models. 1. Introduction. 2. Design errors. 3. Explicit design error models. 4. Implicit error model precursors. 5. Additive implicit error model. 6. Design error detection and correction. 7. Conclusions.
6: Design verification by AT. 1. Introduction. 2. Detecting small AT errors. 3. Bounding error by Walsh transform. 4. Experimental results. 5. Conclusions.
7: Identifying redundant gate and wire replacements. 1. Introduction. 2. Gate replacement faults. 3. Redundancy detection by don't cares. 4.Exact redundant fault identification. 5. Identifying redundant wire replacements. 6. Exact wire redundancy identification. 7. I/O port replacement detection. 8. Experimental results. 9. Conclusions. Conclusions and furtherwork. 1. Conclusions. 2. Future work.
Appendices. References. Index.