AK Sharma
John Wiley & Sons
e druk, 2002
9780780310001
Semiconductor Memories – Technology, Testing and Reliability
Technology, Testing, and Reliability
Specificaties
Gebonden, 480 blz.
|
Engels
John Wiley & Sons |
e druk, 2002
ISBN13: 9780780310001
Rubricering
Levertijd ongeveer 8 werkdagen
Samenvatting
Semiconductor Memories provides in–depth coverage in the areas of design for testing, fault tolerance, failure modes and mechanisms, and screening and qualification methods including.
∗ Memory cell structures and fabrication technologies.
∗ Application–specific memories and architectures.
∗ Memory design, fault modeling and test algorithms, limitations, and trade–offs.
∗ Space environment, radiation hardening process and design techniques, and radiation testing.
∗ Memory stacks and multichip modules for gigabyte storage.
Specificaties
Inhoudsopgave
Preface.
<p>Chapter 1: Introduction.</p>
<p>Chapter 2: Random Access Memory Technologies.</p>
<p>2.1 Introduction.</p>
<p>2.2 Static Random Access Memories (SRAMs).</p>
<p>2.3 Dynamic Random Access Memories (DRAMs).</p>
<p>Chapter 3: Nonvolatile Memories.</p>
<p>3.1 Introduction.</p>
<p>3.2 Masked Read–Only Memories (ROMs).</p>
<p>3.3 Programmable Read–Only Memories (PROMs).</p>
<p>3.4 Erasable (UV)–Programmable Read–Only Memories (EPROMs).</p>
<p>3.5 Electrically Erasable PROMs (EEPROMs).</p>
<p>3.6 Flash Memories (EPROMs or EEPROMs).</p>
<p>Chapter 4: Memory Fault Modeling and Testing.</p>
<p>4.1 Introduction . . . .</p>
<p>4.2 RAM Fault Modeling.</p>
<p>4.3 RAM Electrical Testing.</p>
<p>4.4 RAM Pseudorandom Testing.</p>
<p>4.5 Megabit DRAM Testing.</p>
<p>4.6 Nonvolatile Memory Modeling and Testing.</p>
<p>4.7 IDDQ Fault Modeling and Testing.</p>
<p>4.8 Application Specific Memory Testing.</p>
<p>Chapter 5: Memory Design for Testability and Fault Tolerance.</p>
<p>5.1 General Design for Testability Techniques.</p>
<p>5.2 RAM Built–in Self–Test (BIST).</p>
<p>5.3 Embedded Memory DFT and BIST Techniques.</p>
<p>5.4 Advanced BIST and Built–in Self–Repair Architectures.</p>
<p>5.5 DFT and BIST for ROMs.</p>
<p>5.6 Memory Error–Detection and Correction Techniques.</p>
<p>5.7 Memory Fault–Tolerance Designs.</p>
<p>Chapter 6: Semiconductor Memory Reliability.</p>
<p>6.1 General Reliability Issues.</p>
<p>6.2 RAM Failure Modes and Mechanisms.</p>
<p>6.3 Nonvolatile Memory Reliability.</p>
<p>6.4 Reliability Modeling and Failure Rate Prediction.</p>
<p>6.5 Design for Reliability.</p>
<p>6.6 Reliability Test Structures.</p>
<p>6.7 Reliability Screening and Qualification.</p>
<p>Chapter 7: Semiconductor Memory Radiation Effects.</p>
<p>7.1 Introduction.</p>
<p>7.2 Radiation Effects.</p>
<p>7.3 Radiation–Hardening Techniques.</p>
<p>7.4 Radiation Hardness Assurance and Testing.</p>
<p>Chapter 8: Advanced Memory Technologies.</p>
<p>8.1 Introduction.</p>
<p>8.2 Ferroelectric Random Access Memories (FRAMs).</p>
<p>8.3 Gallium Arsenide (GaAs) FRAMs.</p>
<p>8.4 Analog Memories.</p>
<p>8.5 Magnetoresistive Random Access Memories (MRAMs).</p>
<p>8.6 Experimental Memory Devices.</p>
<p>Chapter 9: High–Density Memory Packaging Technologies.</p>
<p>9.1 Introduction.</p>
<p>9.2 Memory Hybrids and MCMs (2–D).</p>
<p>9.3 Memory Stacks and MCMs (3–D).</p>
<p>9.4 Memory MCM Testing and Reliability Issues.</p>
<p>9.5 Memory Cards.</p>
<p>9.6 High–Density Memory Packaging Future Directions.</p>
<p>Index.</p>
<p>Chapter 1: Introduction.</p>
<p>Chapter 2: Random Access Memory Technologies.</p>
<p>2.1 Introduction.</p>
<p>2.2 Static Random Access Memories (SRAMs).</p>
<p>2.3 Dynamic Random Access Memories (DRAMs).</p>
<p>Chapter 3: Nonvolatile Memories.</p>
<p>3.1 Introduction.</p>
<p>3.2 Masked Read–Only Memories (ROMs).</p>
<p>3.3 Programmable Read–Only Memories (PROMs).</p>
<p>3.4 Erasable (UV)–Programmable Read–Only Memories (EPROMs).</p>
<p>3.5 Electrically Erasable PROMs (EEPROMs).</p>
<p>3.6 Flash Memories (EPROMs or EEPROMs).</p>
<p>Chapter 4: Memory Fault Modeling and Testing.</p>
<p>4.1 Introduction . . . .</p>
<p>4.2 RAM Fault Modeling.</p>
<p>4.3 RAM Electrical Testing.</p>
<p>4.4 RAM Pseudorandom Testing.</p>
<p>4.5 Megabit DRAM Testing.</p>
<p>4.6 Nonvolatile Memory Modeling and Testing.</p>
<p>4.7 IDDQ Fault Modeling and Testing.</p>
<p>4.8 Application Specific Memory Testing.</p>
<p>Chapter 5: Memory Design for Testability and Fault Tolerance.</p>
<p>5.1 General Design for Testability Techniques.</p>
<p>5.2 RAM Built–in Self–Test (BIST).</p>
<p>5.3 Embedded Memory DFT and BIST Techniques.</p>
<p>5.4 Advanced BIST and Built–in Self–Repair Architectures.</p>
<p>5.5 DFT and BIST for ROMs.</p>
<p>5.6 Memory Error–Detection and Correction Techniques.</p>
<p>5.7 Memory Fault–Tolerance Designs.</p>
<p>Chapter 6: Semiconductor Memory Reliability.</p>
<p>6.1 General Reliability Issues.</p>
<p>6.2 RAM Failure Modes and Mechanisms.</p>
<p>6.3 Nonvolatile Memory Reliability.</p>
<p>6.4 Reliability Modeling and Failure Rate Prediction.</p>
<p>6.5 Design for Reliability.</p>
<p>6.6 Reliability Test Structures.</p>
<p>6.7 Reliability Screening and Qualification.</p>
<p>Chapter 7: Semiconductor Memory Radiation Effects.</p>
<p>7.1 Introduction.</p>
<p>7.2 Radiation Effects.</p>
<p>7.3 Radiation–Hardening Techniques.</p>
<p>7.4 Radiation Hardness Assurance and Testing.</p>
<p>Chapter 8: Advanced Memory Technologies.</p>
<p>8.1 Introduction.</p>
<p>8.2 Ferroelectric Random Access Memories (FRAMs).</p>
<p>8.3 Gallium Arsenide (GaAs) FRAMs.</p>
<p>8.4 Analog Memories.</p>
<p>8.5 Magnetoresistive Random Access Memories (MRAMs).</p>
<p>8.6 Experimental Memory Devices.</p>
<p>Chapter 9: High–Density Memory Packaging Technologies.</p>
<p>9.1 Introduction.</p>
<p>9.2 Memory Hybrids and MCMs (2–D).</p>
<p>9.3 Memory Stacks and MCMs (3–D).</p>
<p>9.4 Memory MCM Testing and Reliability Issues.</p>
<p>9.5 Memory Cards.</p>
<p>9.6 High–Density Memory Packaging Future Directions.</p>
<p>Index.</p>