WF Lee
John Wiley & Sons
e druk, 2003
9780471429760
Verilog Coding for Logic Synthesis
Specificaties
Gebonden, 310 blz.
|
Engels
John Wiley & Sons |
e druk, 2003
ISBN13: 9780471429760
Rubricering
Verwachte levertijd ongeveer 9 werkdagen
Samenvatting
Provides a practical approach to Verilog design and problem solving.
∗ Bulk of the book deals with practical design problems that design engineers solve on a daily basis.
∗ Includes over 90 design examples.
∗ There are 3 full scale design examples that include specification, architectural definition, micro–architectural definition, RTL coding, testbench coding and verification.
∗ Book is suitable for use as a textbook in EE departments that have VLSI courses
Specificaties
Inhoudsopgave
Table of Figures.
<p>Table of Examples.</p>
<p>List of Tables.</p>
<p>Preface.</p>
<p>Acknowledgments.</p>
<p>Trademarks.</p>
<p>Introduction.</p>
<p>Asic Design Flow.</p>
<p>Verilog Coding.</p>
<p>Coding Style: Best–Known Method for Synthesis.</p>
<p>Design Example of Programmable Timer.</p>
<p>Design Example of Programmable Logic Block for Peripheral Interface.</p>
<p>Table of Examples.</p>
<p>List of Tables.</p>
<p>Preface.</p>
<p>Acknowledgments.</p>
<p>Trademarks.</p>
<p>Introduction.</p>
<p>Asic Design Flow.</p>
<p>Verilog Coding.</p>
<p>Coding Style: Best–Known Method for Synthesis.</p>
<p>Design Example of Programmable Timer.</p>
<p>Design Example of Programmable Logic Block for Peripheral Interface.</p>