Power Integrity for Nanoscale Integrated Systems

Publisher's Note: Products purchased from Third Party sellers are not guaranteed by the publisher for quality,  authenticity, or access to any online entitlements included with the product.Proven methods for noise-tolerant nanoscale integrated circuit design

This leading-edge guide discusses the impact of power integrity from a design perspective, emphasizing phenomena and problems induced by power integrity degradation and the latest design trends, including low-power design. Power Integrity for Nanoscale Integrated Systems describes how these problems can be forecast early in the design process and the countermeasures that can be used to address them, such as the inclusion of inductance and accurate modeling for PI analysis, as well as robust circuit design. Detailed examples and a case study on the IBM POWER7+ processor illustrate real-world applications of the techniques presented in this practical resource.

Coverage includes: Significance of power integrity for integrated circuitsSupply and substrate noise impact on circuitsClock generation and distribution with power integritySignal and power integrity design for I/O circuitsPower integrity degradation and modelingLumped, distributed, and 3D modeling for power integrityChip temperature and PI impactLow-power techniques and PI impactPower integrity case study using the IBM POWER7+ processor chipCarbon nanotube interconnects for power delivery